#define DKIT_REG_STR(FLD_DEF) (&(_ctc_at_dkit_serdes_field_t)FLD_DEF)

#define DKIT_AT_SERDES_FLD_DEF(reg, hi_bit, lo_bit) { \
    reg, \
    hi_bit, \
    lo_bit, \
    (hi_bit-lo_bit) + 1, \
    (uint32) ((((uint64) 1 << ((hi_bit-lo_bit) + 1)) - 1) << lo_bit), \
    (uint32) ~((((uint64) 1 << ((hi_bit-lo_bit) + 1)) - 1) << lo_bit)}

enum ctc_at_dkit_serdes_type_s
{
    CTC_AT_DKIT_SERDES_56G = 0,
    CTC_AT_DKIT_SERDES_112G,
    CTC_AT_DKIT_SERDES_TYPE_MAX,
};


struct ctc_at_dkit_serdes_dev_s
{
    uint16 serdes_id;
    uint8 lchip;
    uint8 type; /*ctc_at_dkit_serdes_type_t*/
};
typedef struct ctc_at_dkit_serdes_dev_s ctc_at_dkit_serdes_dev_t;

struct _ctc_at_dkit_serdes_field_s
{
    uint32 reg;
    int16  hi_bit;
    int16  lo_bit;
    int16  total_bits;
    uint32 mask;
    uint32 retain_mask;
};
typedef struct _ctc_at_dkit_serdes_field_s _ctc_at_dkit_serdes_field_t;

typedef enum
{
    CTC_AT_DKIT_SERDES_REG_LANE,
    CTC_AT_DKIT_SERDES_REG_GRP,
    CTC_AT_DKIT_SERDES_REG_BUTT
}_ctc_at_dkit_serdes_reg_type_e;

/*HssApbCfg CpuMacHssApbCfg*/
uint32 dkit_apb_cfg_addr[] = {
    0x80064210, 0x800a4210, 0x80164210, 0x801a4210, 0x80264210, 0x802a4210, 0x80364210, 0x803a4210, 
    0x80464210, 0x804a4210, 0x80864210, 0x808a4210, 0x80964210, 0x809a4210, 0x80a64210, 0x80aa4210, 
    0x80b64210, 0x80ba4210, 0x80c64210, 0x80ca4210, 0x81464210, 0x814a4210, 0x81364210, 0x813a4210, 
    0x81264210, 0x812a4210, 0x81164210, 0x811a4210, 0x81064210, 0x810a4210, 0x81c64210, 0x81ca4210, 
    0x81b64210, 0x81ba4210, 0x81a64210, 0x81aa4210, 0x81964210, 0x819a4210, 0x81864210, 0x818a4210, 
    0x85d222c8
};

/*HssApbMon CpuMacHssApbMon*/
uint32 dkit_apb_mon_addr[] = {
    0x80064220, 0x800a4220, 0x80164220, 0x801a4220, 0x80264220, 0x802a4220, 0x80364220, 0x803a4220, 
    0x80464220, 0x804a4220, 0x80864220, 0x808a4220, 0x80964220, 0x809a4220, 0x80a64220, 0x80aa4220, 
    0x80b64220, 0x80ba4220, 0x80c64220, 0x80ca4220, 0x81464220, 0x814a4220, 0x81364220, 0x813a4220, 
    0x81264220, 0x812a4220, 0x81164220, 0x811a4220, 0x81064220, 0x810a4220, 0x81c64220, 0x81ca4220, 
    0x81b64220, 0x81ba4220, 0x81a64220, 0x81aa4220, 0x81964220, 0x819a4220, 0x81864220, 0x818a4220, 
    0x85d222c0
};

/* Define Of Register */
#define F_DKIT_AT112G_PHY_MODE         DKIT_AT_SERDES_FLD_DEF(0xA424, 14, 12)
#define F_DKIT_AT112G_PHY_GEN_TX       DKIT_AT_SERDES_FLD_DEF(0x5530, 17, 8)
#define F_DKIT_AT112G_PHY_GEN_RX       DKIT_AT_SERDES_FLD_DEF(0x5624, 17, 8)
#define F_DKIT_AT112G_REF_FREF_SEL_TX  DKIT_AT_SERDES_FLD_DEF(0x5538, 31, 24)
#define F_DKIT_AT112G_REF_FREF_SEL_RX  DKIT_AT_SERDES_FLD_DEF(0x5630, 7, 0)
#define F_DKIT_AT112G_REFCLK_SEL_TX    DKIT_AT_SERDES_FLD_DEF(0x5538, 22, 22)
#define F_DKIT_AT112G_REFCLK_SEL_RX    DKIT_AT_SERDES_FLD_DEF(0x5634, 30, 30)
#define F_DKIT_AT112G_TX_SEL_BITS      DKIT_AT_SERDES_FLD_DEF(0x3034, 31, 31)
#define F_DKIT_AT112G_RX_SEL_BITS      DKIT_AT_SERDES_FLD_DEF(0x3204, 31, 31)
#define F_DKIT_AT112G_TXD_INV          DKIT_AT_SERDES_FLD_DEF(0x3024, 30, 30)
#define F_DKIT_AT112G_RXD_INV          DKIT_AT_SERDES_FLD_DEF(0x3248, 29, 29)
#define F_DKIT_AT112G_ANA_TX2RX_LPBK   DKIT_AT_SERDES_FLD_DEF(0x1014, 3, 3)      /* LOCAL_ANA_TX2RX_LPBK_EN_LANE */
#define F_DKIT_AT112G_DIG_RX2TX_LPBK   DKIT_AT_SERDES_FLD_DEF(0x3024, 31, 31)    /* LOCAL_DIG_RX2TX_LPBK_EN_LANE */
#define F_DKIT_AT112G_DIG_TX2RX_LPBK   DKIT_AT_SERDES_FLD_DEF(0x3248, 31, 31)    /* LOCAL_DIG_TX2RX_LPBK_EN_LANE */
#define F_DKIT_AT112G_RX_TRAIN_ENA     DKIT_AT_SERDES_FLD_DEF(0x5630, 22, 22)    /* RX_TRAIN_ENABLE_LANE */
#define F_DKIT_AT112G_RX_TRAIN_COM     DKIT_AT_SERDES_FLD_DEF(0x5020, 4, 4)      /* RX_TRAIN_COMPLETE_LANE */
#define F_DKIT_AT112G_RX_TRAIN_FAI     DKIT_AT_SERDES_FLD_DEF(0x5020, 3, 3)      /* RX_TRAIN_FAILED_LANE */
#define F_DKIT_AT112G_TX_TRAIN_ENA     DKIT_AT_SERDES_FLD_DEF(0x5630, 20, 20)    /* TX_TRAIN_ENABLE_LANE */
#define F_DKIT_AT112G_TX_TRAIN_COM     DKIT_AT_SERDES_FLD_DEF(0x5020, 6, 6)      /* TX_TRAIN_COMPLETE_LANE */
#define F_DKIT_AT112G_TX_TRAIN_FAI     DKIT_AT_SERDES_FLD_DEF(0x5020, 5, 5)      /* TX_TRAIN_FAILED_LANE */
#define F_DKIT_AT112G_TRX_TIMER        DKIT_AT_SERDES_FLD_DEF(0x5018, 31, 16)    /* TRX_TRAIN_TIMER_LANE */
#define F_DKIT_AT112G_RX_TIMER         DKIT_AT_SERDES_FLD_DEF(0x5018, 15, 0)     /* RX_TRAIN_TIMER_LANE */
#define F_DKIT_AT112G_TRX_TIMEOUT_EN   DKIT_AT_SERDES_FLD_DEF(0x5014, 10, 10)    /* TRX_TRAIN_TIMEOUT_EN_LANE */
#define F_DKIT_AT112G_TX_PHYREADY      DKIT_AT_SERDES_FLD_DEF(0x3098, 30, 30)    /* PT_TX_PHYREADY_FORCE_LANE */
#define F_DKIT_AT112G_RX_PHYREADY      DKIT_AT_SERDES_FLD_DEF(0x3264, 22, 22)    /* PT_RX_PHYREADY_FORCE_LANE */
#define F_DKIT_AT112G_TX_EN_MODE       DKIT_AT_SERDES_FLD_DEF(0x3098, 3, 2)      /* PT_TX_EN_MODE_LANE */
#define F_DKIT_AT112G_RX_EN_MODE       DKIT_AT_SERDES_FLD_DEF(0x3264, 31, 30)    /* PT_RX_EN_MODE_LANE */
#define F_DKIT_AT112G_TX_EN            DKIT_AT_SERDES_FLD_DEF(0x3098, 31, 31)    /* PT_TX_EN_LANE */
#define F_DKIT_AT112G_RX_EN            DKIT_AT_SERDES_FLD_DEF(0x3264, 23, 23)    /* PT_RX_EN_LANE */
#define F_DKIT_AT112G_TX_RST           DKIT_AT_SERDES_FLD_DEF(0x3098, 5, 5)      /* PT_TX_RST_LANE */
#define F_DKIT_AT112G_RX_RST           DKIT_AT_SERDES_FLD_DEF(0x3270, 7, 7)      /* PT_RX_RST_LANE */
#define F_DKIT_AT112G_TX_FIR_C0        DKIT_AT_SERDES_FLD_DEF(0x30C8, 29, 24)
#define F_DKIT_AT112G_TX_FIR_C0_F      DKIT_AT_SERDES_FLD_DEF(0x30C8, 30, 30)    /* TX_FIR_C0_FORCE_LANE */
#define F_DKIT_AT112G_TX_FIR_C1        DKIT_AT_SERDES_FLD_DEF(0x30C8, 22, 17)
#define F_DKIT_AT112G_TX_FIR_C1_F      DKIT_AT_SERDES_FLD_DEF(0x30C8, 23, 23)    /* TX_FIR_C1_FORCE_LANE */
#define F_DKIT_AT112G_TX_FIR_C2        DKIT_AT_SERDES_FLD_DEF(0x30C8, 14, 9)
#define F_DKIT_AT112G_TX_FIR_C2_F      DKIT_AT_SERDES_FLD_DEF(0x30C8, 15, 15)    /* TX_FIR_C2_FORCE_LANE */
#define F_DKIT_AT112G_TX_FIR_C3        DKIT_AT_SERDES_FLD_DEF(0x30C8, 6, 1)
#define F_DKIT_AT112G_TX_FIR_C3_F      DKIT_AT_SERDES_FLD_DEF(0x30C8, 7, 7)      /* TX_FIR_C3_FORCE_LANE */
#define F_DKIT_AT112G_TX_FIR_C4        DKIT_AT_SERDES_FLD_DEF(0x30CC, 30, 25)
#define F_DKIT_AT112G_TX_FIR_C4_F      DKIT_AT_SERDES_FLD_DEF(0x30CC, 31, 31)    /* TX_FIR_C4_FORCE_LANE */
#define F_DKIT_AT112G_TX_FIR_C5        DKIT_AT_SERDES_FLD_DEF(0x30CC, 22, 17)
#define F_DKIT_AT112G_TX_FIR_C5_F      DKIT_AT_SERDES_FLD_DEF(0x30CC, 23, 23)    /* TX_FIR_C5_FORCE_LANE */
#define F_DKIT_AT112G_TX_FIR_UPDATE    DKIT_AT_SERDES_FLD_DEF(0x30CC, 8, 8)
#define F_DKIT_AT112G_TX_FIR_UPDATE_F  DKIT_AT_SERDES_FLD_DEF(0x30CC, 7, 7)      /* TX_FIR_UPDATE_FORCE_LANE */
#define F_DKIT_AT112G_ANA_TX_FIR_C0    DKIT_AT_SERDES_FLD_DEF(0x30D0, 29, 24)    /* TO_ANA_TX_FIR_C0_LANE */
#define F_DKIT_AT112G_ANA_TX_FIR_C1    DKIT_AT_SERDES_FLD_DEF(0x30D0, 21, 16)    /* TO_ANA_TX_FIR_C1_LANE */
#define F_DKIT_AT112G_ANA_TX_FIR_C2    DKIT_AT_SERDES_FLD_DEF(0x30D0, 13, 8)     /* TO_ANA_TX_FIR_C2_LANE */
#define F_DKIT_AT112G_ANA_TX_FIR_C3    DKIT_AT_SERDES_FLD_DEF(0x30D0, 5, 0)      /* TO_ANA_TX_FIR_C3_LANE */
#define F_DKIT_AT112G_ANA_TX_FIR_C4    DKIT_AT_SERDES_FLD_DEF(0x30D4, 29, 24)    /* TO_ANA_TX_FIR_C4_LANE */
#define F_DKIT_AT112G_ANA_TX_FIR_C5    DKIT_AT_SERDES_FLD_DEF(0x30D4, 21, 16)    /* TO_ANA_TX_FIR_C5_LANE */
#define F_DKIT_AT112G_TX_FIR_POL_F     DKIT_AT_SERDES_FLD_DEF(0x30CC, 0, 0)      /* TX_FIR_TAP_POL_FORCE_LANE */
#define F_DKIT_AT112G_TX_FIR_POL       DKIT_AT_SERDES_FLD_DEF(0x30CC, 6, 1)      /* TX_FIR_TAP_POL_LANE */
#define F_DKIT_AT112G_TRAIN_CTLE_R     DKIT_AT_SERDES_FLD_DEF(0x6378, 20, 16)    /* RX_TRAIN_CTLE_R_LANE */
#define F_DKIT_AT112G_TRAIN_CTLE_C     DKIT_AT_SERDES_FLD_DEF(0x6378, 15, 8)     /* RX_TRAIN_CTLE_C_LANE */
#define F_DKIT_AT112G_TRAIN_CTLE_GC    DKIT_AT_SERDES_FLD_DEF(0x6378, 4, 0)      /* RX_TRAIN_CTLE_GC_LANE */
#define F_DKIT_AT112G_TRAIN_CTLE_ATTE  DKIT_AT_SERDES_FLD_DEF(0x6374, 31, 24)    /* RX_TRAIN_CTLE_ATTEN_LANE */
#define F_DKIT_AT112G_KP_FRAC          DKIT_AT_SERDES_FLD_DEF(0x4A0C, 30, 29)    /* RX_DTL_LPF_KP_FRAC_LANE */
#define F_DKIT_AT112G_KP_SHIFT         DKIT_AT_SERDES_FLD_DEF(0x4A0C, 28, 25)    /* RX_DTL_LPF_KP_SHIFT_LANE */
#define F_DKIT_AT112G_KI_SHIFT         DKIT_AT_SERDES_FLD_DEF(0x4A0C, 23, 19)    /* RX_DTL_LPF_KI_SHIFT_LANE */
#define F_DKIT_AT112G_KI_FRAC          DKIT_AT_SERDES_FLD_DEF(0x4A0C, 17, 17)    /* RX_DTL_LPF_KI_FRAC_LANE */
#define F_DKIT_AT112G_TX_PATTERN_SEL   DKIT_AT_SERDES_FLD_DEF(0x3098, 29, 24)    /* PT_TX_PATTERN_SEL_LANE */
#define F_DKIT_AT112G_RX_PATTERN_SEL   DKIT_AT_SERDES_FLD_DEF(0x3264, 29, 24)    /* PT_RX_PATTERN_SEL_LANE */
#define F_DKIT_AT112G_TXDATA_PRE_EN    DKIT_AT_SERDES_FLD_DEF(0x5538, 18, 18)    /* TXDATA_PRE_CODE_EN_LANE */
#define F_DKIT_AT112G_TX_UP_79_48      DKIT_AT_SERDES_FLD_DEF(0x309C, 31, 0)     /* PT_TX_USER_PATTERN_LANE[79:48] */
#define F_DKIT_AT112G_TX_UP_47_16      DKIT_AT_SERDES_FLD_DEF(0x30A0, 31, 0)     /* PT_TX_USER_PATTERN_LANE[47:16] */
#define F_DKIT_AT112G_TX_UP_15_0       DKIT_AT_SERDES_FLD_DEF(0x30A4, 31, 16)    /* PT_TX_USER_PATTERN_LANE[15:0] */
#define F_DKIT_AT112G_RXDATA_PRE_EN    DKIT_AT_SERDES_FLD_DEF(0x5634, 26, 26)    /* RXDATA_PRE_CODE_EN_LANE */
#define F_DKIT_AT112G_RX_UP_79_48      DKIT_AT_SERDES_FLD_DEF(0x3268, 31, 0)     /* PT_RX_USER_PATTERN_LANE[79:48] */
#define F_DKIT_AT112G_RX_UP_47_16      DKIT_AT_SERDES_FLD_DEF(0x326C, 31, 0)     /* PT_RX_USER_PATTERN_LANE[47:16] */
#define F_DKIT_AT112G_RX_UP_15_0       DKIT_AT_SERDES_FLD_DEF(0x3270, 31, 16)    /* PT_RX_USER_PATTERN_LANE[15:0] */
#define F_DKIT_AT112G_TXDATA_GRAY_EN   DKIT_AT_SERDES_FLD_DEF(0x5538, 20, 20)    /* TXDATA_GRAY_CODE_EN_LANE */
#define F_DKIT_AT112G_RXDATA_GRAY_EN   DKIT_AT_SERDES_FLD_DEF(0x5634, 28, 28)    /* RXDATA_GRAY_CODE_EN_LANE */
#define F_DKIT_AT112G_TXD_SWAP         DKIT_AT_SERDES_FLD_DEF(0x3024, 18, 18)    /* TXD_MSB_LSB_SWAP_LANE */
#define F_DKIT_AT112G_TXDATA_SWAP      DKIT_AT_SERDES_FLD_DEF(0x3024, 5, 5)      /* TXDATA_MSB_LSB_SWAP_LANE */
#define F_DKIT_AT112G_RXD_SWAP         DKIT_AT_SERDES_FLD_DEF(0x3248, 28, 28)    /* RXD_MSB_LSB_SWAP_LANE */
#define F_DKIT_AT112G_RXDATA_SWAP      DKIT_AT_SERDES_FLD_DEF(0x3248, 25, 25)    /* RXDATA_MSB_LSB_SWAP_LANE */
#define F_DKIT_AT112G_RX_LOCK          DKIT_AT_SERDES_FLD_DEF(0x3270, 0, 0)      /* PT_RX_LOCK_LANE */
#define F_DKIT_AT112G_RX_PASS          DKIT_AT_SERDES_FLD_DEF(0x3270, 1, 1)      /* PT_RX_PASS_LANE */
#define F_DKIT_AT112G_RX_CNT_47_32     DKIT_AT_SERDES_FLD_DEF(0x3274, 31, 16)    /* PT_RX_CNT_LANE[47:32] */
#define F_DKIT_AT112G_RX_CNT_31_0      DKIT_AT_SERDES_FLD_DEF(0x3278, 31, 0)     /* PT_RX_CNT_LANE[31:0] */
#define F_DKIT_AT112G_RX_ERR_47_32     DKIT_AT_SERDES_FLD_DEF(0x327C, 31, 16)    /* PT_RX_ERR_CNT_LANE[47:32] */
#define F_DKIT_AT112G_RX_ERR_31_0      DKIT_AT_SERDES_FLD_DEF(0x3280, 31, 0)     /* PT_RX_ERR_CNT_LANE[31:0] */
#define F_DKIT_AT112G_ESM_EN           DKIT_AT_SERDES_FLD_DEF(0x6054, 18, 18)
#define F_DKIT_AT112G_EOM_READY        DKIT_AT_SERDES_FLD_DEF(0x6110, 8, 8)
#define F_DKIT_AT112G_ESM_VOLTAGE      DKIT_AT_SERDES_FLD_DEF(0x6110, 7, 0)
#define F_DKIT_AT112G_ESM_PHASE        DKIT_AT_SERDES_FLD_DEF(0x6054, 9, 0)
#define F_DKIT_AT112G_EOM_CALL_CONV    DKIT_AT_SERDES_FLD_DEF(0x6110, 9, 9)
#define F_DKIT_AT112G_EOM_CALL         DKIT_AT_SERDES_FLD_DEF(0x6110, 10, 10)
#define F_DKIT_AT112G_EOM_D00_CNT      DKIT_AT_SERDES_FLD_DEF(0x4584, 31, 0)     /* EOM_HIST_D00_CNT_LANE */
#define F_DKIT_AT112G_EOM_D01_CNT      DKIT_AT_SERDES_FLD_DEF(0x4588, 31, 0)     /* EOM_HIST_D01_CNT_LANE */
#define F_DKIT_AT112G_EOM_D10_CNT      DKIT_AT_SERDES_FLD_DEF(0x458c, 31, 0)     /* EOM_HIST_D10_CNT_LANE */
#define F_DKIT_AT112G_EOM_D11_CNT      DKIT_AT_SERDES_FLD_DEF(0x4590, 31, 0)     /* EOM_HIST_D11_CNT_LANE */
#define F_DKIT_AT112G_EOM_N_D00_CNT    DKIT_AT_SERDES_FLD_DEF(0x60B8, 31, 0)     /* EOM_HIST_N_D00_CNT_LANE */
#define F_DKIT_AT112G_EOM_N_D01_CNT    DKIT_AT_SERDES_FLD_DEF(0x60BC, 31, 0)     /* EOM_HIST_N_D01_CNT_LANE */
#define F_DKIT_AT112G_EOM_N_D10_CNT    DKIT_AT_SERDES_FLD_DEF(0x60C0, 31, 0)     /* EOM_HIST_N_D10_CNT_LANE */
#define F_DKIT_AT112G_EOM_N_D11_CNT    DKIT_AT_SERDES_FLD_DEF(0x60C4, 31, 0)     /* EOM_HIST_N_D11_CNT_LANE */
#define F_DKIT_AT112G_EOM_BOT_H_CNT    DKIT_AT_SERDES_FLD_DEF(0x456c, 31, 0)     /* EOM_HIST_BOT_H_CNT_LANE */
#define F_DKIT_AT112G_EOM_BOT_L_CNT    DKIT_AT_SERDES_FLD_DEF(0x4570, 31, 0)     /* EOM_HIST_BOT_L_CNT_LANE */
#define F_DKIT_AT112G_EOM_MID_H_CNT    DKIT_AT_SERDES_FLD_DEF(0x4574, 31, 0)     /* EOM_HIST_MID_H_CNT_LANE */
#define F_DKIT_AT112G_EOM_MID_L_CNT    DKIT_AT_SERDES_FLD_DEF(0x4578, 31, 0)     /* EOM_HIST_MID_L_CNT_LANE */
#define F_DKIT_AT112G_EOM_TOP_H_CNT    DKIT_AT_SERDES_FLD_DEF(0x457c, 31, 0)     /* EOM_HIST_TOP_H_CNT_LANE */
#define F_DKIT_AT112G_EOM_TOP_L_CNT    DKIT_AT_SERDES_FLD_DEF(0x4580, 31, 0)     /* EOM_HIST_TOP_L_CNT_LANE */
#define F_DKIT_AT112G_EOM_N_BOT_H_CNT  DKIT_AT_SERDES_FLD_DEF(0x60A0, 31, 0)     /* EOM_HIST_N_BOT_H_CNT_LANE */
#define F_DKIT_AT112G_EOM_N_BOT_L_CNT  DKIT_AT_SERDES_FLD_DEF(0x60A4, 31, 0)     /* EOM_HIST_N_BOT_L_CNT_LANE */
#define F_DKIT_AT112G_EOM_N_MID_H_CNT  DKIT_AT_SERDES_FLD_DEF(0x60A8, 31, 0)     /* EOM_HIST_N_MID_H_CNT_LANE */
#define F_DKIT_AT112G_EOM_N_MID_L_CNT  DKIT_AT_SERDES_FLD_DEF(0x60AC, 31, 0)     /* EOM_HIST_N_MID_L_CNT_LANE */
#define F_DKIT_AT112G_EOM_N_TOP_H_CNT  DKIT_AT_SERDES_FLD_DEF(0x60B0, 31, 0)     /* EOM_HIST_N_TOP_H_CNT_LANE */
#define F_DKIT_AT112G_EOM_N_TOP_L_CNT  DKIT_AT_SERDES_FLD_DEF(0x60B4, 31, 0)     /* EOM_HIST_N_TOP_L_CNT_LANE */
#define F_DKIT_AT112G_RX_DATA_WIDTH    DKIT_AT_SERDES_FLD_DEF(0x323C, 2, 1)
#define F_DKIT_AT112G_DP_PRE6          DKIT_AT_SERDES_FLD_DEF(0x4860, 2, 0)      /* RX_DP_LMS_FFE_PRE6_COE_LANE */
#define F_DKIT_AT112G_DP_PRE5          DKIT_AT_SERDES_FLD_DEF(0x485C, 2, 0)      /* RX_DP_LMS_FFE_PRE5_COE_LANE */
#define F_DKIT_AT112G_DP_PRE4          DKIT_AT_SERDES_FLD_DEF(0x4858, 4, 0)      /* RX_DP_LMS_FFE_PRE4_COE_LANE */
#define F_DKIT_AT112G_DP_PRE3          DKIT_AT_SERDES_FLD_DEF(0x4854, 4, 0)      /* RX_DP_LMS_FFE_PRE3_COE_LANE */
#define F_DKIT_AT112G_DP_PRE2          DKIT_AT_SERDES_FLD_DEF(0x4850, 5, 0)      /* RX_DP_LMS_FFE_PRE2_COE_LANE */
#define F_DKIT_AT112G_DP_PRE1          DKIT_AT_SERDES_FLD_DEF(0x484C, 6, 0)      /* RX_DP_LMS_FFE_PRE1_COE_LANE */
#define F_DKIT_AT112G_DP_PST1          DKIT_AT_SERDES_FLD_DEF(0x486C, 6, 0)      /* RX_DP_LMS_FFE_PST1_COE_LANE */
#define F_DKIT_AT112G_DP_PST2          DKIT_AT_SERDES_FLD_DEF(0x4870, 5, 0)      /* RX_DP_LMS_FFE_PST2_COE_LANE */
#define F_DKIT_AT112G_DP_PST3          DKIT_AT_SERDES_FLD_DEF(0x4874, 4, 0)      /* RX_DP_LMS_FFE_PST3_COE_LANE */
#define F_DKIT_AT112G_DP_PST4          DKIT_AT_SERDES_FLD_DEF(0x4878, 4, 0)      /* RX_DP_LMS_FFE_PST4_COE_LANE */
#define F_DKIT_AT112G_DP_PST5          DKIT_AT_SERDES_FLD_DEF(0x487C, 4, 0)      /* RX_DP_LMS_FFE_PST5_COE_LANE */
#define F_DKIT_AT112G_DP_PST6          DKIT_AT_SERDES_FLD_DEF(0x4880, 4, 0)      /* RX_DP_LMS_FFE_PST6_COE_LANE */
#define F_DKIT_AT112G_DP_PST7          DKIT_AT_SERDES_FLD_DEF(0x4884, 3, 0)      /* RX_DP_LMS_FFE_PST7_COE_LANE */
#define F_DKIT_AT112G_DP_PST8          DKIT_AT_SERDES_FLD_DEF(0x4888, 3, 0)      /* RX_DP_LMS_FFE_PST8_COE_LANE */
#define F_DKIT_AT112G_DP_PST9          DKIT_AT_SERDES_FLD_DEF(0x488C, 2, 0)      /* RX_DP_LMS_FFE_PST9_COE_LANE */
#define F_DKIT_AT112G_DP_PST10         DKIT_AT_SERDES_FLD_DEF(0x4890, 2, 0)      /* RX_DP_LMS_FFE_PST10_COE_LANE */
#define F_DKIT_AT112G_DP_PST11         DKIT_AT_SERDES_FLD_DEF(0x4894, 2, 0)      /* RX_DP_LMS_FFE_PST11_COE_LANE */
#define F_DKIT_AT112G_DP_PST12         DKIT_AT_SERDES_FLD_DEF(0x4898, 2, 0)      /* RX_DP_LMS_FFE_PST12_COE_LANE */
#define F_DKIT_AT112G_DP_PST13         DKIT_AT_SERDES_FLD_DEF(0x489C, 2, 0)      /* RX_DP_LMS_FFE_PST13_COE_LANE */
#define F_DKIT_AT112G_DP_PST14         DKIT_AT_SERDES_FLD_DEF(0x48A0, 2, 0)      /* RX_DP_LMS_FFE_PST14_COE_LANE */
#define F_DKIT_AT112G_DP_PST15         DKIT_AT_SERDES_FLD_DEF(0x48A4, 2, 0)      /* RX_DP_LMS_FFE_PST15_COE_LANE */
#define F_DKIT_AT112G_DP_PST16         DKIT_AT_SERDES_FLD_DEF(0x48A8, 2, 0)      /* RX_DP_LMS_FFE_PST16_COE_LANE */
#define F_DKIT_AT112G_DP_GAIN          DKIT_AT_SERDES_FLD_DEF(0x48E0, 10, 0)     /* RX_DP_LMS_GAIN_COE_LANE */
#define F_DKIT_AT112G_DP_BLW           DKIT_AT_SERDES_FLD_DEF(0x4810, 5, 0)      /* RX_DP_LMS_BLW_COE_LANE */
#define F_DKIT_AT112G_DP_DFE           DKIT_AT_SERDES_FLD_DEF(0x48E8, 5, 0)      /* RX_DP_LMS_DFE_COE_LANE */
#define F_DKIT_AT112G_DTL_PRE3         DKIT_AT_SERDES_FLD_DEF(0x4A4C, 3, 0)      /* RX_DTL_LMS_FFE_PRE3_COE_LANE */
#define F_DKIT_AT112G_DTL_PRE2         DKIT_AT_SERDES_FLD_DEF(0x4A48, 4, 0)      /* RX_DTL_LMS_FFE_PRE2_COE_LANE */
#define F_DKIT_AT112G_DTL_PRE1         DKIT_AT_SERDES_FLD_DEF(0x4A44, 5, 0)      /* RX_DTL_LMS_FFE_PRE1_COE_LANE */
#define F_DKIT_AT112G_DTL_PST1         DKIT_AT_SERDES_FLD_DEF(0x4A50, 5, 0)      /* RX_DTL_LMS_FFE_PST1_COE_LANE */
#define F_DKIT_AT112G_DTL_PST2         DKIT_AT_SERDES_FLD_DEF(0x4A54, 4, 0)      /* RX_DTL_LMS_FFE_PST2_COE_LANE */
#define F_DKIT_AT112G_DTL_PST3         DKIT_AT_SERDES_FLD_DEF(0x4A58, 3, 0)      /* RX_DTL_LMS_FFE_PST3_COE_LANE */
#define F_DKIT_AT112G_DTL_GAIN         DKIT_AT_SERDES_FLD_DEF(0x4A40, 9, 0)      /* RX_DTL_LMS_GAIN_COE_LANE */
#define F_DKIT_AT112G_DTL_BLW          DKIT_AT_SERDES_FLD_DEF(0x4A38, 4, 0)      /* RX_DTL_LMS_BLW_COE_LANE */
#define F_DKIT_AT112G_AVDD_SEL         DKIT_AT_SERDES_FLD_DEF(0xA420, 28, 26)
#define F_DKIT_AT112G_SPD_CFG          DKIT_AT_SERDES_FLD_DEF(0xA424, 7, 4)
#define F_DKIT_AT112G_LANE_SEL         DKIT_AT_SERDES_FLD_DEF(0xA318, 31, 28)
#define F_DKIT_AT112G_FW_MAJOR_VER     DKIT_AT_SERDES_FLD_DEF(0xE600, 31, 24)
#define F_DKIT_AT112G_FW_MINOR_VER     DKIT_AT_SERDES_FLD_DEF(0xE600, 23, 16)
#define F_DKIT_AT112G_FW_PATCH_VER     DKIT_AT_SERDES_FLD_DEF(0xE600, 15, 8)
#define F_DKIT_AT112G_FW_BUILD_VER     DKIT_AT_SERDES_FLD_DEF(0xE600, 7, 0)
#define F_DKIT_AT112G_PLL_TS_LOCK_RD   DKIT_AT_SERDES_FLD_DEF(0x5700, 6, 6)      /* ANA_PLL_TS_LOCK_RD_LANE */
#define F_DKIT_AT112G_PLL_RS_LOCK_RD   DKIT_AT_SERDES_FLD_DEF(0x5800, 30, 30)    /* ANA_PLL_RS_LOCK_RD_LANE */
#define F_DKIT_AT112G_PLL_READY_TX     DKIT_AT_SERDES_FLD_DEF(0x3000, 20, 20)
#define F_DKIT_AT112G_PLL_READY_RX     DKIT_AT_SERDES_FLD_DEF(0x3200, 24, 24)
#define F_DKIT_AT112G_RX_INIT          DKIT_AT_SERDES_FLD_DEF(0x5630, 24, 24)
#define F_DKIT_AT112G_RX_INIT_DONE     DKIT_AT_SERDES_FLD_DEF(0x3200, 19, 19)
#define F_DKIT_AT112G_RX_CDR_LOCK      DKIT_AT_SERDES_FLD_DEF(0x4A00, 10, 10)
#define F_DKIT_AT112G_BROADCAST        DKIT_AT_SERDES_FLD_DEF(0xA318, 27, 27)
#define F_DKIT_AT112G_PU_PLL           DKIT_AT_SERDES_FLD_DEF(0x5530, 6, 6)
#define F_DKIT_AT112G_PU_TX            DKIT_AT_SERDES_FLD_DEF(0x5530, 4, 4)
#define F_DKIT_AT112G_PU_RX            DKIT_AT_SERDES_FLD_DEF(0x5624, 6, 6)
#define F_DKIT_AT112G_MCU_FREQ         DKIT_AT_SERDES_FLD_DEF(0xA420, 15, 0)
#define F_DKIT_AT112G_TX_IDLE          DKIT_AT_SERDES_FLD_DEF(0x3014, 18, 18)
#define F_DKIT_AT112G_PU_IVREF         DKIT_AT_SERDES_FLD_DEF(0xA424, 2, 2)
#define F_DKIT_AT112G_PU_IVREF_FM_REG  DKIT_AT_SERDES_FLD_DEF(0xA424, 1, 1)
#define F_DKIT_AT112G_SQ_RES_RD        DKIT_AT_SERDES_FLD_DEF(0x181C, 6, 1)      /* SQ_CAL_RESULT_RD_LANE */
#define F_DKIT_AT112G_SQ_RES_EXT       DKIT_AT_SERDES_FLD_DEF(0x1818, 7, 2)      /* SQ_CAL_RESULT_EXT_LANE */
#define F_DKIT_AT112G_SQ_INDV_EXT_EN   DKIT_AT_SERDES_FLD_DEF(0x1810, 0, 0)      /* SQ_CAL_INDV_EXT_EN_LANE */
#define F_DKIT_AT112G_SQ_OUT_LPF_RD    DKIT_AT_SERDES_FLD_DEF(0x3260, 14, 14)    /* PIN_RX_SQ_OUT_LPF_RD_LANE */
#define F_DKIT_AT112G_TSEN_ADC_DATA    DKIT_AT_SERDES_FLD_DEF(0xA32C, 15, 0)
#define F_DKIT_AT112G_ADD_ERR_EN       DKIT_AT_SERDES_FLD_DEF(0x3024, 29, 29)
#define F_DKIT_AT112G_ADD_ERR_NUM      DKIT_AT_SERDES_FLD_DEF(0x3024, 28, 26)
#define F_DKIT_AT112G_RX_CNT_RST       DKIT_AT_SERDES_FLD_DEF(0x3264, 21, 21)    /* PT_RX_CNT_RST_LANE */
#define F_DKIT_AT112G_CLI_CMD          DKIT_AT_SERDES_FLD_DEF(0x6064, 7, 0)
#define F_DKIT_AT112G_CLI_ARGS         DKIT_AT_SERDES_FLD_DEF(0x6064, 31, 16)
#define F_DKIT_AT112G_CLI_START        DKIT_AT_SERDES_FLD_DEF(0x6064, 8, 8)
#define F_DKIT_AT112G_RX_DP_TOP_EN     DKIT_AT_SERDES_FLD_DEF(0x4808, 4, 4)      /* RX_DP_LMS_TOP_EN_LANE */
#define F_DKIT_AT112G_RX_DTL_TOP_EN    DKIT_AT_SERDES_FLD_DEF(0x4A30, 4, 4)      /* RX_DTL_LMS_TOP_EN_LANE */
#define F_DKIT_AT112G_EQ_MON_CLK_EN    DKIT_AT_SERDES_FLD_DEF(0x401C, 7, 7)      /* RX_EQ_MON_CLK_EN_LANE */
#define F_DKIT_AT112G_MSE_START        DKIT_AT_SERDES_FLD_DEF(0x45A0, 29, 29)
#define F_DKIT_AT112G_MSE_DONE         DKIT_AT_SERDES_FLD_DEF(0x45B0, 8, 8)
#define F_DKIT_AT112G_MSE_EN           DKIT_AT_SERDES_FLD_DEF(0x45A0, 31, 31)
#define F_DKIT_AT112G_MSE_ADAPT_EN     DKIT_AT_SERDES_FLD_DEF(0x45A0, 14, 14)    /* MSE_ANI_ADAPT_EN_LANE */
#define F_DKIT_AT112G_MSE_MODE         DKIT_AT_SERDES_FLD_DEF(0x45A0, 21, 21)
#define F_DKIT_AT112G_MSE_CONT_MODE    DKIT_AT_SERDES_FLD_DEF(0x45A0, 28, 28)
#define F_DKIT_AT112G_MSE_RD_REQ       DKIT_AT_SERDES_FLD_DEF(0x45A0, 23, 23)
#define F_DKIT_AT112G_MSE_RD_ACK       DKIT_AT_SERDES_FLD_DEF(0x45B0, 9, 9)
#define F_DKIT_AT112G_MSE_VAL          DKIT_AT_SERDES_FLD_DEF(0x45AC, 31, 16)
#define F_DKIT_AT112G_RX_PAM2_EN       DKIT_AT_SERDES_FLD_DEF(0x3208, 0, 0)
#define F_DKIT_AT112G_PHY_ISOLATE      DKIT_AT_SERDES_FLD_DEF(0xA318, 23, 23)    /* PHY_ISOLATE_MODE */
#define F_DKIT_AT112G_BG_RDY           DKIT_AT_SERDES_FLD_DEF(0xA420, 24, 24)
#define F_DKIT_AT112G_FW_READY         DKIT_AT_SERDES_FLD_DEF(0xA428, 14, 14)
#define F_DKIT_AT112G_MCU_INIT_DONE    DKIT_AT_SERDES_FLD_DEF(0xA200, 7, 7)
#define F_DKIT_AT112G_TRX_TRAIN_TO_EN  DKIT_AT_SERDES_FLD_DEF(0x5014, 10, 10)    /* TRX_TRAIN_TIMEOUT_EN_LANE */
#define F_DKIT_AT112G_PLL_SEL_LANE     DKIT_AT_SERDES_FLD_DEF(0x607c, 9, 8)      /* PLL_SEL_LANE */

#define F_DKIT_AT56G_LANE_SEL          DKIT_AT_SERDES_FLD_DEF(0xA318, 31, 28)
#define F_DKIT_AT56G_DFE_EN            DKIT_AT_SERDES_FLD_DEF(0x5648, 29, 29)
#define F_DKIT_AT56G_RSRVD_INPUT_RX_RD DKIT_AT_SERDES_FLD_DEF(0x5604, 15, 0)     /* PIN_RESERVED_INPUT_RX_RD_LANE */
#define F_DKIT_AT56G_RSRVD_INPUT_RX    DKIT_AT_SERDES_FLD_DEF(0x562C, 31, 16)    /* RESERVED_INPUT_RX_LANE */
#define F_DKIT_AT56G_RSRVD_INPUT_RX_FM DKIT_AT_SERDES_FLD_DEF(0x562C, 15, 15)    /* RESERVED_INPUT_RX_FM_REG_LANE */
#define F_DKIT_AT56G_BROADCAST         DKIT_AT_SERDES_FLD_DEF(0xA318, 27, 27)
#define F_DKIT_AT56G_PLL_RS_LOCK       DKIT_AT_SERDES_FLD_DEF(0x5800, 30, 30)
#define F_DKIT_AT56G_PLL_TS_LOCK       DKIT_AT_SERDES_FLD_DEF(0x5700, 6, 6)
#define F_DKIT_AT56G_PH_OS_DAT         DKIT_AT_SERDES_FLD_DEF(0x6DDC, 7, 0)
#define F_DKIT_AT56G_ALIGN90_CAL_7_0   DKIT_AT_SERDES_FLD_DEF(0x19B8, 7, 0)      /* RX_ALIGN90_CAL_SETTING_LANE[7:0] */
#define F_DKIT_AT56G_SQ_RES_RD         DKIT_AT_SERDES_FLD_DEF(0x1AF0, 6, 1)
#define F_DKIT_AT56G_SQ_RES_EXT        DKIT_AT_SERDES_FLD_DEF(0x1AEC, 7, 2)
#define F_DKIT_AT56G_SQ_INDV           DKIT_AT_SERDES_FLD_DEF(0x1AE4, 0, 0)
#define F_DKIT_AT56G_TX_SEL_BITS       DKIT_AT_SERDES_FLD_DEF(0x3034, 31, 31)
#define F_DKIT_AT56G_RX_SEL_BITS       DKIT_AT_SERDES_FLD_DEF(0x3204, 31, 31)
#define F_DKIT_AT56G_TX_PAM2_EN        DKIT_AT_SERDES_FLD_DEF(0x303C, 30, 30)
#define F_DKIT_AT56G_RX_PAM2_EN        DKIT_AT_SERDES_FLD_DEF(0x3204, 0, 0)
#define F_DKIT_AT56G_RX_ANA_PAM2_EN    DKIT_AT_SERDES_FLD_DEF(0x3204, 28, 28)
#define F_DKIT_AT56G_RX_EQ_PAM2_EN     DKIT_AT_SERDES_FLD_DEF(0x3204, 29, 29)
#define F_DKIT_AT56G_TXD_INV           DKIT_AT_SERDES_FLD_DEF(0x3024, 30, 30)
#define F_DKIT_AT56G_RXD_INV           DKIT_AT_SERDES_FLD_DEF(0x3248, 29, 29)
#define F_DKIT_AT56G_FW_MAJOR_VER      DKIT_AT_SERDES_FLD_DEF(0xE600, 31, 24)
#define F_DKIT_AT56G_FW_MINOR_VER      DKIT_AT_SERDES_FLD_DEF(0xE600, 23, 16)
#define F_DKIT_AT56G_FW_PATCH_VER      DKIT_AT_SERDES_FLD_DEF(0xE600, 15, 8)
#define F_DKIT_AT56G_FW_BUILD_VER      DKIT_AT_SERDES_FLD_DEF(0xE600, 7, 0)
#define F_DKIT_AT56G_TX_C0             DKIT_AT_SERDES_FLD_DEF(0x30CC, 29, 24)
#define F_DKIT_AT56G_TX_C1             DKIT_AT_SERDES_FLD_DEF(0x30CC, 22, 17)
#define F_DKIT_AT56G_TX_C2             DKIT_AT_SERDES_FLD_DEF(0x30CC, 14, 9)
#define F_DKIT_AT56G_TX_C3             DKIT_AT_SERDES_FLD_DEF(0x30CC, 6, 1)
#define F_DKIT_AT56G_TX_C4             DKIT_AT_SERDES_FLD_DEF(0x30D0, 30, 25)
#define F_DKIT_AT56G_TX_C5             DKIT_AT_SERDES_FLD_DEF(0x30D0, 22, 17)
#define F_DKIT_AT56G_TX_C0_FORCE       DKIT_AT_SERDES_FLD_DEF(0x30CC, 30, 30)
#define F_DKIT_AT56G_TX_C1_FORCE       DKIT_AT_SERDES_FLD_DEF(0x30CC, 23, 23)
#define F_DKIT_AT56G_TX_C2_FORCE       DKIT_AT_SERDES_FLD_DEF(0x30CC, 15, 15)
#define F_DKIT_AT56G_TX_C3_FORCE       DKIT_AT_SERDES_FLD_DEF(0x30CC, 7, 7)
#define F_DKIT_AT56G_TX_C4_FORCE       DKIT_AT_SERDES_FLD_DEF(0x30D0, 31, 31)
#define F_DKIT_AT56G_TX_C5_FORCE       DKIT_AT_SERDES_FLD_DEF(0x30D0, 23, 23)
#define F_DKIT_AT56G_TX_UP             DKIT_AT_SERDES_FLD_DEF(0x30D0, 8, 8)
#define F_DKIT_AT56G_TX_UP_FORCE       DKIT_AT_SERDES_FLD_DEF(0x30D0, 7, 7)
#define F_DKIT_AT56G_ANA_TX_C0         DKIT_AT_SERDES_FLD_DEF(0x30D4, 29, 24)
#define F_DKIT_AT56G_ANA_TX_C1         DKIT_AT_SERDES_FLD_DEF(0x30D4, 21, 16)
#define F_DKIT_AT56G_ANA_TX_C2         DKIT_AT_SERDES_FLD_DEF(0x30D4, 13, 8)
#define F_DKIT_AT56G_ANA_TX_C3         DKIT_AT_SERDES_FLD_DEF(0x30D4, 5, 0)
#define F_DKIT_AT56G_ANA_TX_C4         DKIT_AT_SERDES_FLD_DEF(0x30D8, 29, 24)
#define F_DKIT_AT56G_ANA_TX_C5         DKIT_AT_SERDES_FLD_DEF(0x30D8, 21, 16)
#define F_DKIT_AT56G_TX_FIR_TAP_POL    DKIT_AT_SERDES_FLD_DEF(0x30D0, 6, 1)
#define F_DKIT_AT56G_TX_FIR_TAP_POL_F  DKIT_AT_SERDES_FLD_DEF(0x30D0, 0, 0)      /* TX_FIR_TAP_POL_FORCE_LANE */
#define F_DKIT_AT56G_TO_ANA_TX_FIR_POL DKIT_AT_SERDES_FLD_DEF(0x30D8, 13, 8)     /* TO_ANA_TX_FIR_TAP_POL_LANE */
#define F_DKIT_AT56G_ADD_ERR_EN        DKIT_AT_SERDES_FLD_DEF(0x3024, 29, 29)
#define F_DKIT_AT56G_ADD_ERR_NUM       DKIT_AT_SERDES_FLD_DEF(0x3024, 28, 26)
#define F_DKIT_AT56G_CURRENT1_SEL      DKIT_AT_SERDES_FLD_DEF(0x1050, 3, 0)
#define F_DKIT_AT56G_RL1_SEL           DKIT_AT_SERDES_FLD_DEF(0x1060, 3, 0)
#define F_DKIT_AT56G_RL1_EXTRA         DKIT_AT_SERDES_FLD_DEF(0x1038, 2, 0)
#define F_DKIT_AT56G_RES1_SEL          DKIT_AT_SERDES_FLD_DEF(0x1058, 3, 0)
#define F_DKIT_AT56G_CAP1_SEL_G        DKIT_AT_SERDES_FLD_DEF(0x1048, 3, 0)
#define F_DKIT_AT56G_EN_MID_FREQ       DKIT_AT_SERDES_FLD_DEF(0x1088, 4, 4)
#define F_DKIT_AT56G_CS1_MID           DKIT_AT_SERDES_FLD_DEF(0x1040, 5, 4)
#define F_DKIT_AT56G_RS1_MID           DKIT_AT_SERDES_FLD_DEF(0x1040, 7, 6)
#define F_DKIT_AT56G_CURRENT2_SEL      DKIT_AT_SERDES_FLD_DEF(0x1054, 3, 0)
#define F_DKIT_AT56G_RL2_SEL           DKIT_AT_SERDES_FLD_DEF(0x1064, 3, 0)
#define F_DKIT_AT56G_RL2_TUNE_G        DKIT_AT_SERDES_FLD_DEF(0x0100, 2, 0)
#define F_DKIT_AT56G_RES2_SEL          DKIT_AT_SERDES_FLD_DEF(0x105C, 3, 0)
#define F_DKIT_AT56G_CAP2_SEL          DKIT_AT_SERDES_FLD_DEF(0x104C, 3, 0)
#define F_DKIT_AT56G_CTLE_CL1_SEL      DKIT_AT_SERDES_FLD_DEF(0x103C, 1, 0)
#define F_DKIT_AT56G_CTLE_CL2_SEL      DKIT_AT_SERDES_FLD_DEF(0x103C, 3, 2)
#define F_DKIT_AT56G_RX_SELMUFI        DKIT_AT_SERDES_FLD_DEF(0x3200, 3, 0)
#define F_DKIT_AT56G_RX_SELMUFF        DKIT_AT_SERDES_FLD_DEF(0x3200, 7, 4)
#define F_DKIT_AT56G_REG_SELMUPI       DKIT_AT_SERDES_FLD_DEF(0x10CC, 2, 0)
#define F_DKIT_AT56G_REG_SELMUPF       DKIT_AT_SERDES_FLD_DEF(0x10C4, 2, 0)
#define F_DKIT_AT56G_DC_D_T_E_SM       DKIT_AT_SERDES_FLD_DEF(0x4108, 22, 16)
#define F_DKIT_AT56G_DC_E_E_SM         DKIT_AT_SERDES_FLD_DEF(0x410C, 22, 16)
#define F_DKIT_AT56G_VREF_T_E_SM       DKIT_AT_SERDES_FLD_DEF(0x4110, 14, 8)
#define F_DKIT_AT56G_F0_D_T_E_SM       DKIT_AT_SERDES_FLD_DEF(0x4114, 5, 0)
#define F_DKIT_AT56G_F1_D_T_E_SM       DKIT_AT_SERDES_FLD_DEF(0x4118, 22, 16)
#define F_DKIT_AT56G_F1P5_E_SM         DKIT_AT_SERDES_FLD_DEF(0x4140, 13, 8)
#define F_DKIT_AT56G_F2_D_T_E_SM       DKIT_AT_SERDES_FLD_DEF(0x4120, 5, 0)
#define F_DKIT_AT56G_F3_T_E_SM         DKIT_AT_SERDES_FLD_DEF(0x4124, 22, 16)
#define F_DKIT_AT56G_F4_T_E_SM         DKIT_AT_SERDES_FLD_DEF(0x4128, 14, 8)
#define F_DKIT_AT56G_F5_LSB_E_SM       DKIT_AT_SERDES_FLD_DEF(0x4128, 21, 16)
#define F_DKIT_AT56G_F5_MSB_E_SM       DKIT_AT_SERDES_FLD_DEF(0x4128, 29, 24)
#define F_DKIT_AT56G_F6_LSB_E_SM       DKIT_AT_SERDES_FLD_DEF(0x412C, 5, 0)
#define F_DKIT_AT56G_F6_MSB_E_SM       DKIT_AT_SERDES_FLD_DEF(0x412C, 13, 8)
#define F_DKIT_AT56G_F7_LSB_E_SM       DKIT_AT_SERDES_FLD_DEF(0x412C, 21, 16)
#define F_DKIT_AT56G_F7_MSB_E_SM       DKIT_AT_SERDES_FLD_DEF(0x412C, 29, 24)
#define F_DKIT_AT56G_F8_LSB_E_SM       DKIT_AT_SERDES_FLD_DEF(0x4130, 13, 8)
#define F_DKIT_AT56G_F8_MSB_E_SM       DKIT_AT_SERDES_FLD_DEF(0x4130, 21, 16)
#define F_DKIT_AT56G_F9_LSB_E_SM       DKIT_AT_SERDES_FLD_DEF(0x4134, 5, 0)
#define F_DKIT_AT56G_F9_MSB_E_SM       DKIT_AT_SERDES_FLD_DEF(0x4134, 13, 8)
#define F_DKIT_AT56G_F10_LSB_E_SM      DKIT_AT_SERDES_FLD_DEF(0x4134, 29, 24)
#define F_DKIT_AT56G_F10_MSB_E_SM      DKIT_AT_SERDES_FLD_DEF(0x4138, 5, 0)
#define F_DKIT_AT56G_F11_E_SM          DKIT_AT_SERDES_FLD_DEF(0x4138, 20, 16)
#define F_DKIT_AT56G_F12_E_SM          DKIT_AT_SERDES_FLD_DEF(0x413C, 4, 0)
#define F_DKIT_AT56G_F13_E_SM          DKIT_AT_SERDES_FLD_DEF(0x413C, 20, 16)
#define F_DKIT_AT56G_F14_E_SM          DKIT_AT_SERDES_FLD_DEF(0x413C, 28, 24)
#define F_DKIT_AT56G_F15_E_SM          DKIT_AT_SERDES_FLD_DEF(0x4140, 4, 0)
#define F_DKIT_AT56G_FF0_E_SM          DKIT_AT_SERDES_FLD_DEF(0x4130, 5, 0)
#define F_DKIT_AT56G_FF1_E_SM          DKIT_AT_SERDES_FLD_DEF(0x4130, 29, 24)
#define F_DKIT_AT56G_FF2_E_SM          DKIT_AT_SERDES_FLD_DEF(0x4134, 21, 16)
#define F_DKIT_AT56G_FF3_E_SM          DKIT_AT_SERDES_FLD_DEF(0x4138, 13, 8)
#define F_DKIT_AT56G_FF4_E_SM          DKIT_AT_SERDES_FLD_DEF(0x4138, 29, 24)
#define F_DKIT_AT56G_FF5_E_SM          DKIT_AT_SERDES_FLD_DEF(0x413C, 13, 8)
#define F_DKIT_AT56G_DC_D_M_E_SM       DKIT_AT_SERDES_FLD_DEF(0x4108, 14, 8)
#define F_DKIT_AT56G_VREF_M_E_SM       DKIT_AT_SERDES_FLD_DEF(0x4110, 6, 0)
#define F_DKIT_AT56G_F0_D_M_E_SM       DKIT_AT_SERDES_FLD_DEF(0x4110, 29, 24)
#define F_DKIT_AT56G_F1_D_M_E_SM       DKIT_AT_SERDES_FLD_DEF(0x4118, 14, 8)
#define F_DKIT_AT56G_F2_D_M_E_SM       DKIT_AT_SERDES_FLD_DEF(0x411C, 29, 24)
#define F_DKIT_AT56G_F3_M_E_SM         DKIT_AT_SERDES_FLD_DEF(0x4124, 14, 8)
#define F_DKIT_AT56G_F4_M_E_SM         DKIT_AT_SERDES_FLD_DEF(0x4128, 6, 0)
#define F_DKIT_AT56G_DC_D_B_E_SM       DKIT_AT_SERDES_FLD_DEF(0x4108, 6, 0)
#define F_DKIT_AT56G_VREF_B_E_SM       DKIT_AT_SERDES_FLD_DEF(0x410C, 30, 24)
#define F_DKIT_AT56G_F0_D_B_E_SM       DKIT_AT_SERDES_FLD_DEF(0x4110, 21, 16)
#define F_DKIT_AT56G_F1_D_B_E_SM       DKIT_AT_SERDES_FLD_DEF(0x4118, 6, 0)
#define F_DKIT_AT56G_F2_D_B_E_SM       DKIT_AT_SERDES_FLD_DEF(0x411C, 21, 16)
#define F_DKIT_AT56G_F3_B_E_SM         DKIT_AT_SERDES_FLD_DEF(0x4124, 6, 0)
#define F_DKIT_AT56G_F4_B_E_SM         DKIT_AT_SERDES_FLD_DEF(0x4124, 30, 24)
#define F_DKIT_AT56G_F0_DC_SHIFT       DKIT_AT_SERDES_FLD_DEF(0x1088, 6, 5)
#define F_DKIT_AT56G_DFE_RES_F0        DKIT_AT_SERDES_FLD_DEF(0x106C, 5, 4)
#define F_DKIT_AT56G_DFE_F0_RES_DOUBLE DKIT_AT_SERDES_FLD_DEF(0x1068, 3, 3)
#define F_DKIT_AT56G_F0_D_T_O_2C       DKIT_AT_SERDES_FLD_DEF(0x418C, 7, 0)
#define F_DKIT_AT56G_F0_S_T_O_2C       DKIT_AT_SERDES_FLD_DEF(0x418C, 31, 24)
#define F_DKIT_AT56G_F0_D_T_E_2C       DKIT_AT_SERDES_FLD_DEF(0x41C8, 7, 0)
#define F_DKIT_AT56G_F0_S_T_E_2C       DKIT_AT_SERDES_FLD_DEF(0x41C8, 31, 24)
#define F_DKIT_AT56G_F0_D_M_O_2C       DKIT_AT_SERDES_FLD_DEF(0x4188, 31, 24)
#define F_DKIT_AT56G_F0_S_M_O_2C       DKIT_AT_SERDES_FLD_DEF(0x418C, 23, 16)
#define F_DKIT_AT56G_F0_D_M_E_2C       DKIT_AT_SERDES_FLD_DEF(0x41C4, 31, 24)
#define F_DKIT_AT56G_F0_S_M_E_2C       DKIT_AT_SERDES_FLD_DEF(0x41C8, 23, 16)
#define F_DKIT_AT56G_F0_D_B_O_2C       DKIT_AT_SERDES_FLD_DEF(0x4188, 23, 16)
#define F_DKIT_AT56G_F0_S_B_O_2C       DKIT_AT_SERDES_FLD_DEF(0x418C, 15, 8)
#define F_DKIT_AT56G_F0_D_B_E_2C       DKIT_AT_SERDES_FLD_DEF(0x41C4, 23, 16)
#define F_DKIT_AT56G_F0_S_B_E_2C       DKIT_AT_SERDES_FLD_DEF(0x41C8, 15, 8)
#define F_DKIT_AT56G_DFE_ADAPT         DKIT_AT_SERDES_FLD_DEF(0x4000, 13, 13)
#define F_DKIT_AT56G_CLI_CMD           DKIT_AT_SERDES_FLD_DEF(0x6068, 7, 0)
#define F_DKIT_AT56G_CLI_ARGS          DKIT_AT_SERDES_FLD_DEF(0x606C, 31, 0)
#define F_DKIT_AT56G_CLI_START         DKIT_AT_SERDES_FLD_DEF(0x6068, 8, 8)
#define F_DKIT_AT56G_DFE_F0X_SEL       DKIT_AT_SERDES_FLD_DEF(0x401C, 14, 10)
#define F_DKIT_AT56G_DFE_LOAD_EN       DKIT_AT_SERDES_FLD_DEF(0x6DD0, 15, 15)
#define F_DKIT_AT56G_TRX_TIMER         DKIT_AT_SERDES_FLD_DEF(0x5018, 31, 16)
#define F_DKIT_AT56G_RX_TIMER          DKIT_AT_SERDES_FLD_DEF(0x5018, 15, 0)
#define F_DKIT_AT56G_TX_TIMER_EN       DKIT_AT_SERDES_FLD_DEF(0x6034, 29, 29)
#define F_DKIT_AT56G_RX_TIMER_EN       DKIT_AT_SERDES_FLD_DEF(0x6034, 30, 30)
#define F_DKIT_AT56G_D_TX2RX_LPBK      DKIT_AT_SERDES_FLD_DEF(0x3248, 31, 31)
#define F_DKIT_AT56G_A_TX2RX_LPBK      DKIT_AT_SERDES_FLD_DEF(0x1130, 3, 3)
#define F_DKIT_AT56G_D_RX2TX_LPBK      DKIT_AT_SERDES_FLD_DEF(0x3024, 31, 31)
#define F_DKIT_AT56G_DTL_CLAMPING      DKIT_AT_SERDES_FLD_DEF(0x3260, 26, 24)    /* DTL_CLAMPING_SEL */
#define F_DKIT_AT56G_R2T_NO_STOP       DKIT_AT_SERDES_FLD_DEF(0x3024, 25, 25)    /* RX2TX_FIFO_NO_STOP */
#define F_DKIT_AT56G_R2T_RD_START      DKIT_AT_SERDES_FLD_DEF(0x3024, 24, 24)    /* RX2TX_FIFO_RD_START_POINT */
#define F_DKIT_AT56G_FOFFSET_DIS       DKIT_AT_SERDES_FLD_DEF(0x3268, 16, 16)    /* RX_FOFFSET_DISABLE */
#define F_DKIT_AT56G_PU_LB             DKIT_AT_SERDES_FLD_DEF(0x10B8, 3, 3)
#define F_DKIT_AT56G_DTL_SQ_DET_EN     DKIT_AT_SERDES_FLD_DEF(0x3260, 13, 13)
#define F_DKIT_AT56G_DFE_SQ_EN         DKIT_AT_SERDES_FLD_DEF(0x4040, 29, 29)
#define F_DKIT_AT56G_CLI_START         DKIT_AT_SERDES_FLD_DEF(0x6068, 8, 8)
#define F_DKIT_AT56G_TX_PAT_SEL        DKIT_AT_SERDES_FLD_DEF(0x3098, 29, 24)
#define F_DKIT_AT56G_RX_PAT_SEL        DKIT_AT_SERDES_FLD_DEF(0x3280, 29, 24)
#define F_DKIT_AT56G_TXD_SWAP          DKIT_AT_SERDES_FLD_DEF(0x3024, 18, 18)
#define F_DKIT_AT56G_TXDATA_SWAP       DKIT_AT_SERDES_FLD_DEF(0x3024, 5, 5)
#define F_DKIT_AT56G_RXD_SWAP          DKIT_AT_SERDES_FLD_DEF(0x3248, 27, 27)
#define F_DKIT_AT56G_RXDATA_SWAP       DKIT_AT_SERDES_FLD_DEF(0x3248, 24, 24)
#define F_DKIT_AT56G_RX_CNT_4732       DKIT_AT_SERDES_FLD_DEF(0x3290, 31, 16)
#define F_DKIT_AT56G_RX_CNT_3100       DKIT_AT_SERDES_FLD_DEF(0x3294, 31, 0)
#define F_DKIT_AT56G_RX_ERR_4732       DKIT_AT_SERDES_FLD_DEF(0x3298, 31, 16)
#define F_DKIT_AT56G_RX_ERR_3100       DKIT_AT_SERDES_FLD_DEF(0x329C, 31, 0)
#define F_DKIT_AT56G_TX_UP_7948        DKIT_AT_SERDES_FLD_DEF(0x309C, 31, 0)
#define F_DKIT_AT56G_TX_UP_4716        DKIT_AT_SERDES_FLD_DEF(0x30A0, 31, 0)
#define F_DKIT_AT56G_TX_UP_1500        DKIT_AT_SERDES_FLD_DEF(0x30A4, 31, 16)
#define F_DKIT_AT56G_RX_UP_7948        DKIT_AT_SERDES_FLD_DEF(0x3284, 31, 0)
#define F_DKIT_AT56G_RX_UP_4716        DKIT_AT_SERDES_FLD_DEF(0x3288, 31, 0)
#define F_DKIT_AT56G_RX_UP_1500        DKIT_AT_SERDES_FLD_DEF(0x328C, 31, 16)
#define F_DKIT_AT56G_TX_PHYREADY       DKIT_AT_SERDES_FLD_DEF(0x3098, 30, 30)
#define F_DKIT_AT56G_RX_PHYREADY       DKIT_AT_SERDES_FLD_DEF(0x3280, 22, 22)
#define F_DKIT_AT56G_TX_EN_MODE        DKIT_AT_SERDES_FLD_DEF(0x3098, 3, 2)
#define F_DKIT_AT56G_RX_EN_MODE        DKIT_AT_SERDES_FLD_DEF(0x3280, 31, 30)
#define F_DKIT_AT56G_TX_EN             DKIT_AT_SERDES_FLD_DEF(0x3098, 31, 31)
#define F_DKIT_AT56G_RX_EN             DKIT_AT_SERDES_FLD_DEF(0x3280, 23, 23)
#define F_DKIT_AT56G_TRX_EN            DKIT_AT_SERDES_FLD_DEF(0x328C, 8, 8)
#define F_DKIT_AT56G_TX_RST            DKIT_AT_SERDES_FLD_DEF(0x3098, 5, 5)
#define F_DKIT_AT56G_RX_RST            DKIT_AT_SERDES_FLD_DEF(0x328C, 7, 7)
#define F_DKIT_AT56G_RX_LOCK           DKIT_AT_SERDES_FLD_DEF(0x328C, 0, 0)
#define F_DKIT_AT56G_RX_PASS           DKIT_AT_SERDES_FLD_DEF(0x328C, 1, 1)
#define F_DKIT_AT56G_RX_CNT_RST        DKIT_AT_SERDES_FLD_DEF(0x3280, 21, 21)
#define F_DKIT_AT56G_DFE_RATE          DKIT_AT_SERDES_FLD_DEF(0x4010, 9, 8)
#define F_DKIT_AT56G_DFE_UP_DIS        DKIT_AT_SERDES_FLD_DEF(0x5648, 25, 25)    /* DFE_UPDATE_DIS_LANE */
#define F_DKIT_AT56G_TRAIN_DONE        DKIT_AT_SERDES_FLD_DEF(0x608C, 0, 0)
#define F_DKIT_AT56G_MCU_DEBUGF        DKIT_AT_SERDES_FLD_DEF(0x34F4, 31, 24)
#define F_DKIT_AT56G_DFE_SAT_EN        DKIT_AT_SERDES_FLD_DEF(0x4040, 31, 30)
#define F_DKIT_AT56G_TSEN_DATA         DKIT_AT_SERDES_FLD_DEF(0xA32C, 15, 0)
#define F_DKIT_AT56G_ESM_PATH_SEL      DKIT_AT_SERDES_FLD_DEF(0x6058, 16, 16)
#define F_DKIT_AT56G_ESM_DFEADAPT      DKIT_AT_SERDES_FLD_DEF(0x6058, 13, 10)
#define F_DKIT_AT56G_ADAPT_EVEN        DKIT_AT_SERDES_FLD_DEF(0x6DE4, 8, 8)
#define F_DKIT_AT56G_ADAPT_ODD         DKIT_AT_SERDES_FLD_DEF(0x6DE4, 9, 9)
#define F_DKIT_AT56G_ESM_EN            DKIT_AT_SERDES_FLD_DEF(0x6058, 18, 18)
#define F_DKIT_AT56G_EOM_READY         DKIT_AT_SERDES_FLD_DEF(0x603C, 3, 3)
#define F_DKIT_AT56G_ESM_LPNUM         DKIT_AT_SERDES_FLD_DEF(0x6078, 15, 0)
#define F_DKIT_AT56G_ESM_PHASE         DKIT_AT_SERDES_FLD_DEF(0x6078, 26, 16)
#define F_DKIT_AT56G_ESM_VOLTAGE       DKIT_AT_SERDES_FLD_DEF(0x603C, 15, 8)
#define F_DKIT_AT56G_EOM_DFE_CALL      DKIT_AT_SERDES_FLD_DEF(0x603C, 4, 4)
#define F_DKIT_AT56G_VC_T_P_3100       DKIT_AT_SERDES_FLD_DEF(0x4220, 31, 0)     /* EOM_VLD_CNT_TOP_P [31:00] */
#define F_DKIT_AT56G_VC_T_P_3932       DKIT_AT_SERDES_FLD_DEF(0x4238, 23, 16)
#define F_DKIT_AT56G_VC_T_N_3100       DKIT_AT_SERDES_FLD_DEF(0x422C, 31, 0)
#define F_DKIT_AT56G_VC_T_N_3932       DKIT_AT_SERDES_FLD_DEF(0x423C, 23, 16)
#define F_DKIT_AT56G_VC_M_P_3100       DKIT_AT_SERDES_FLD_DEF(0x4224, 31, 0)
#define F_DKIT_AT56G_VC_M_P_3932       DKIT_AT_SERDES_FLD_DEF(0x4238, 15, 8)
#define F_DKIT_AT56G_VC_M_N_3100       DKIT_AT_SERDES_FLD_DEF(0x4230, 31, 0)
#define F_DKIT_AT56G_VC_M_N_3932       DKIT_AT_SERDES_FLD_DEF(0x423C, 15, 8)
#define F_DKIT_AT56G_VC_B_P_3100       DKIT_AT_SERDES_FLD_DEF(0x4228, 31, 0)
#define F_DKIT_AT56G_VC_B_P_3932       DKIT_AT_SERDES_FLD_DEF(0x4238, 7, 0)
#define F_DKIT_AT56G_VC_B_N_3100       DKIT_AT_SERDES_FLD_DEF(0x4234, 31, 0)
#define F_DKIT_AT56G_VC_B_N_3932       DKIT_AT_SERDES_FLD_DEF(0x423C, 7, 0)
#define F_DKIT_AT56G_EOM_EC_T_P        DKIT_AT_SERDES_FLD_DEF(0x4200, 31, 0)
#define F_DKIT_AT56G_EOM_EC_T_N        DKIT_AT_SERDES_FLD_DEF(0x420C, 31, 0)
#define F_DKIT_AT56G_EOM_EC_M_P        DKIT_AT_SERDES_FLD_DEF(0x4204, 31, 0)
#define F_DKIT_AT56G_EOM_EC_M_N        DKIT_AT_SERDES_FLD_DEF(0x4210, 31, 0)
#define F_DKIT_AT56G_EOM_EC_B_P        DKIT_AT_SERDES_FLD_DEF(0x4208, 31, 0)
#define F_DKIT_AT56G_EOM_EC_B_N        DKIT_AT_SERDES_FLD_DEF(0x4214, 31, 0)
#define F_DKIT_AT56G_PHY_ISOLATE       DKIT_AT_SERDES_FLD_DEF(0xA318, 23, 23)    /* PHY_ISOLATE_MODE */
#define F_DKIT_AT56G_FW_READY          DKIT_AT_SERDES_FLD_DEF(0xA424, 14, 14)
#define F_DKIT_AT56G_MCU_INIT_DONE     DKIT_AT_SERDES_FLD_DEF(0xA200, 7, 7)
#define F_DKIT_AT56G_BG_RDY            DKIT_AT_SERDES_FLD_DEF(0xA41C, 24, 24)
#define F_DKIT_AT56G_RX_INIT           DKIT_AT_SERDES_FLD_DEF(0x5630, 24, 24)
#define F_DKIT_AT56G_RX_INIT_DONE      DKIT_AT_SERDES_FLD_DEF(0x3200, 19, 19)
#define F_DKIT_AT56G_PU_IVREF          DKIT_AT_SERDES_FLD_DEF(0xA420, 2, 2)
#define F_DKIT_AT56G_PU_IVREF_FM_REG   DKIT_AT_SERDES_FLD_DEF(0xA420, 1, 1)
#define F_DKIT_AT56G_PU_TX             DKIT_AT_SERDES_FLD_DEF(0x5530, 13, 13)
#define F_DKIT_AT56G_ANA_PU_TX         DKIT_AT_SERDES_FLD_DEF(0x3000, 30, 30)
#define F_DKIT_AT56G_ANA_PU_TX_FORCE   DKIT_AT_SERDES_FLD_DEF(0x3000, 31, 31)
#define F_DKIT_AT56G_PU_RX             DKIT_AT_SERDES_FLD_DEF(0x5624, 8, 8)
#define F_DKIT_AT56G_ANA_PU_RX         DKIT_AT_SERDES_FLD_DEF(0x3200, 30, 30)
#define F_DKIT_AT56G_ANA_PU_RX_FORCE   DKIT_AT_SERDES_FLD_DEF(0x3200, 31, 31)
#define F_DKIT_AT56G_PU_PLL            DKIT_AT_SERDES_FLD_DEF(0x5530, 15, 15)
#define F_DKIT_AT56G_TX_IDLE           DKIT_AT_SERDES_FLD_DEF(0x3014, 18, 18)
#define F_DKIT_AT56G_PHY_MODE          DKIT_AT_SERDES_FLD_DEF(0xA420, 14, 12)
#define F_DKIT_AT56G_REF_FREF_TX       DKIT_AT_SERDES_FLD_DEF(0x5538, 23, 19)    /* REF_FREF_SEL_TX_LANE */
#define F_DKIT_AT56G_REF_FREF_RX       DKIT_AT_SERDES_FLD_DEF(0x5634, 30, 26)    /* REF_FREF_SEL_RX_LANE */
#define F_DKIT_AT56G_REFCLK_SEL_TX     DKIT_AT_SERDES_FLD_DEF(0x5538, 17, 17)
#define F_DKIT_AT56G_REFCLK_SEL_RX     DKIT_AT_SERDES_FLD_DEF(0x5634, 24, 24)
#define F_DKIT_AT56G_PHY_GEN_TX        DKIT_AT_SERDES_FLD_DEF(0x5530, 22, 17)
#define F_DKIT_AT56G_PHY_GEN_RX        DKIT_AT_SERDES_FLD_DEF(0x5624, 15, 10)
#define F_DKIT_AT56G_MCU_FREQ          DKIT_AT_SERDES_FLD_DEF(0xA41C, 15, 0)
#define F_DKIT_AT56G_RX_TRAIN_ENA      DKIT_AT_SERDES_FLD_DEF(0x5630, 22, 22)
#define F_DKIT_AT56G_RX_TRAIN_COM      DKIT_AT_SERDES_FLD_DEF(0x5020, 4, 4)
#define F_DKIT_AT56G_RX_TRAIN_FAI      DKIT_AT_SERDES_FLD_DEF(0x5020, 3, 3)
#define F_DKIT_AT56G_TX_TRAIN_ENA      DKIT_AT_SERDES_FLD_DEF(0x5630, 16, 16)
#define F_DKIT_AT56G_TX_TRAIN_COM      DKIT_AT_SERDES_FLD_DEF(0x5020, 6, 6)
#define F_DKIT_AT56G_TX_TRAIN_FAI      DKIT_AT_SERDES_FLD_DEF(0x5020, 5, 5)
#define F_DKIT_AT56G_RX_SQ_OUT         DKIT_AT_SERDES_FLD_DEF(0x3270, 14, 14)
#define F_DKIT_AT56G_AVDD_SEL          DKIT_AT_SERDES_FLD_DEF(0xA41C, 28, 26)
#define F_DKIT_AT56G_SPD_CFG           DKIT_AT_SERDES_FLD_DEF(0xA420, 7, 4)
#define F_DKIT_AT56G_TX_GRAY_EN        DKIT_AT_SERDES_FLD_DEF(0x3098, 6, 6)
#define F_DKIT_AT56G_RX_GRAY_EN        DKIT_AT_SERDES_FLD_DEF(0x3280, 15, 15)
#define F_DKIT_AT56G_TXDATA_PRECODE_EN DKIT_AT_SERDES_FLD_DEF(0x5538, 13, 13)    /* TXDATA_PRE_CODE_EN_LANE */
#define F_DKIT_AT56G_RXDATA_PRECODE_EN DKIT_AT_SERDES_FLD_DEF(0x5644, 28, 28)    /* RXDATA_PRE_CODE_EN_LANE */
#define F_DKIT_AT56G_PLL_READY_TX      DKIT_AT_SERDES_FLD_DEF(0x3000, 20, 20)
#define F_DKIT_AT56G_PLL_READY_RX      DKIT_AT_SERDES_FLD_DEF(0x3200, 24, 24)
#define F_DKIT_AT56G_RESET_CORE_TX     DKIT_AT_SERDES_FLD_DEF(0x5538, 28, 28)
#define F_DKIT_AT56G_RESET_CORE_RX     DKIT_AT_SERDES_FLD_DEF(0x5630, 0, 0)
#define F_DKIT_AT56G_RESET_CORE_ACK_TX DKIT_AT_SERDES_FLD_DEF(0x3000, 21, 21)    /* RESET_CORE_ACK_TX_LANE */
#define F_DKIT_AT56G_RESET_CORE_ACK_RX DKIT_AT_SERDES_FLD_DEF(0x321C, 2, 2)      /* RESET_CORE_ACK_RX_LANE */
#define F_DKIT_AT56G_MCU_REMOTE_CMD    DKIT_AT_SERDES_FLD_DEF(0x5638, 31, 0)     /* MCU_REMOTE_COMMAND_LANE */
#define F_DKIT_AT56G_MCU_REMOTE_CMD_FM DKIT_AT_SERDES_FLD_DEF(0x563C, 31, 31)    /* MCU_REMOTE_COMMAND_FM_REG_LANE */
#define F_DKIT_AT56G_MCU_REMOTE_CMD_RD DKIT_AT_SERDES_FLD_DEF(0x5618, 31, 0)     /* PIN_MCU_REMOTE_COMMAND_RD_LANE */
#define F_DKIT_AT56G_MCU_REMOTE_STA    DKIT_AT_SERDES_FLD_DEF(0x5640, 31, 0)
#define F_DKIT_AT56G_MCU_REMOTE_STA_FM DKIT_AT_SERDES_FLD_DEF(0x5644, 31, 31)    /* MCU_REMOTE_STATUS_FM_REG_LANE */
#define F_DKIT_AT56G_MCU_REMOTE_STA_RD DKIT_AT_SERDES_FLD_DEF(0x5620, 31, 0)     /* PIN_MCU_REMOTE_STATUS_RD_LANE */
#define F_DKIT_AT56G_MCU_REMOTE_REQ    DKIT_AT_SERDES_FLD_DEF(0x563C, 30, 30)
#define F_DKIT_AT56G_MCU_REMOTE_REQ_FM DKIT_AT_SERDES_FLD_DEF(0x563C, 29, 29)    /* MCU_REMOTE_REQ_FM_REG_LANE */
#define F_DKIT_AT56G_MCU_REMOTE_REQ_RD DKIT_AT_SERDES_FLD_DEF(0x561C, 31, 31)    /* PIN_MCU_REMOTE_REQ_RD_LANE */
#define F_DKIT_AT56G_MCU_LOCAL_ACK     DKIT_AT_SERDES_FLD_DEF(0x3530, 16, 16)
#define F_DKIT_AT56G_MCU_LOCAL_STATUS  DKIT_AT_SERDES_FLD_DEF(0x3534, 31, 0)
#define F_DKIT_AT56G_PTN_LOCK_LOST_TO  DKIT_AT_SERDES_FLD_DEF(0x5014, 24, 24)    /* PATTERN_LOCK_LOST_TIMEOUT_EN_LANE */
#define F_DKIT_AT56G_TRX_TRAIN_TO_EN   DKIT_AT_SERDES_FLD_DEF(0x5014, 10, 10)    /* TRX_TRAIN_TIMEOUT_EN_LANE */
#define F_DKIT_AT56G_PLL_SEL_LANE      DKIT_AT_SERDES_FLD_DEF(0x607c, 9, 8)      /* PLL_SEL_LANE */

typedef enum
{
    DKIT_AT56G_PIN_RESET        = 0,
    DKIT_AT56G_PIN_ISOLATION       ,    /* PIN_ISOLATION_ENB */
    DKIT_AT56G_PIN_BG_RDY          ,
    DKIT_AT56G_PIN_SIF_SEL         ,
    DKIT_AT56G_PIN_MCU_CLK         ,
    DKIT_AT56G_PIN_DIRECTACCES     ,    /* PIN_DIRECT_ACCESS_EN */
    DKIT_AT56G_PIN_PHY_MODE        ,
    DKIT_AT56G_PIN_REFCLK_TX0      ,    /* PIN_REFCLK_SEL_TX0 */
    DKIT_AT56G_PIN_REFCLK_TX1      ,    /* PIN_REFCLK_SEL_TX1 */
    DKIT_AT56G_PIN_REFCLK_TX2      ,    /* PIN_REFCLK_SEL_TX2 */
    DKIT_AT56G_PIN_REFCLK_TX3      ,   /* PIN_REFCLK_SEL_TX3 */
    DKIT_AT56G_PIN_REFCLK_RX0      ,   /* PIN_REFCLK_SEL_RX0 */
    DKIT_AT56G_PIN_REFCLK_RX1      ,   /* PIN_REFCLK_SEL_RX1 */
    DKIT_AT56G_PIN_REFCLK_RX2      ,   /* PIN_REFCLK_SEL_RX2 */
    DKIT_AT56G_PIN_REFCLK_RX3      ,   /* PIN_REFCLK_SEL_RX3 */
    DKIT_AT56G_PIN_REFFREF_TX0     ,   /* PIN_REF_FREF_SEL_TX0 */
    DKIT_AT56G_PIN_REFFREF_TX1     ,   /* PIN_REF_FREF_SEL_TX1 */
    DKIT_AT56G_PIN_REFFREF_TX2     ,   /* PIN_REF_FREF_SEL_TX2 */
    DKIT_AT56G_PIN_REFFREF_TX3     ,   /* PIN_REF_FREF_SEL_TX3 */
    DKIT_AT56G_PIN_REFFREF_RX0     ,   /* PIN_REF_FREF_SEL_RX0 */
    DKIT_AT56G_PIN_REFFREF_RX1     ,   /* PIN_REF_FREF_SEL_RX1 */
    DKIT_AT56G_PIN_REFFREF_RX2     ,   /* PIN_REF_FREF_SEL_RX2 */
    DKIT_AT56G_PIN_REFFREF_RX3     ,   /* PIN_REF_FREF_SEL_RX3 */
    DKIT_AT56G_PIN_PHY_GEN_TX0     ,
    DKIT_AT56G_PIN_PHY_GEN_TX1     ,
    DKIT_AT56G_PIN_PHY_GEN_TX2     ,
    DKIT_AT56G_PIN_PHY_GEN_TX3     ,
    DKIT_AT56G_PIN_PHY_GEN_RX0     ,
    DKIT_AT56G_PIN_PHY_GEN_RX1     ,
    DKIT_AT56G_PIN_PHY_GEN_RX2     ,
    DKIT_AT56G_PIN_PHY_GEN_RX3     ,
    DKIT_AT56G_PIN_PU_PLL0         ,
    DKIT_AT56G_PIN_PU_PLL1         ,
    DKIT_AT56G_PIN_PU_PLL2         ,
    DKIT_AT56G_PIN_PU_PLL3         ,
    DKIT_AT56G_PIN_PU_RX0          ,
    DKIT_AT56G_PIN_PU_RX1          ,
    DKIT_AT56G_PIN_PU_RX2          ,
    DKIT_AT56G_PIN_PU_RX3          ,
    DKIT_AT56G_PIN_PU_TX0          ,
    DKIT_AT56G_PIN_PU_TX1          ,
    DKIT_AT56G_PIN_PU_TX2          ,
    DKIT_AT56G_PIN_PU_TX3          ,
    DKIT_AT56G_PIN_TX_IDLE0        ,
    DKIT_AT56G_PIN_TX_IDLE1        ,
    DKIT_AT56G_PIN_TX_IDLE2        ,
    DKIT_AT56G_PIN_TX_IDLE3        ,
    DKIT_AT56G_PIN_PU_IVREF        ,
    DKIT_AT56G_PIN_RX_TRAINEN0     ,   /* PIN_RX_TRAIN_ENABLE0 */
    DKIT_AT56G_PIN_RX_TRAINEN1     ,   /* PIN_RX_TRAIN_ENABLE1 */
    DKIT_AT56G_PIN_RX_TRAINEN2     ,   /* PIN_RX_TRAIN_ENABLE2 */
    DKIT_AT56G_PIN_RX_TRAINEN3     ,   /* PIN_RX_TRAIN_ENABLE3 */
    DKIT_AT56G_PIN_RX_TRAINCO0     ,   /* PIN_RX_TRAIN_COMPLETE0 */
    DKIT_AT56G_PIN_RX_TRAINCO1     ,   /* PIN_RX_TRAIN_COMPLETE1 */
    DKIT_AT56G_PIN_RX_TRAINCO2     ,   /* PIN_RX_TRAIN_COMPLETE2 */
    DKIT_AT56G_PIN_RX_TRAINCO3     ,   /* PIN_RX_TRAIN_COMPLETE3 */
    DKIT_AT56G_PIN_RX_TRAINFA0     ,   /* PIN_RX_TRAIN_FAILED0 */
    DKIT_AT56G_PIN_RX_TRAINFA1     ,   /* PIN_RX_TRAIN_FAILED1 */
    DKIT_AT56G_PIN_RX_TRAINFA2     ,   /* PIN_RX_TRAIN_FAILED2 */
    DKIT_AT56G_PIN_RX_TRAINFA3     ,   /* PIN_RX_TRAIN_FAILED3 */
    DKIT_AT56G_PIN_TX_TRAINEN0     ,   /* PIN_TX_TRAIN_ENABLE0 */
    DKIT_AT56G_PIN_TX_TRAINEN1     ,   /* PIN_TX_TRAIN_ENABLE1 */
    DKIT_AT56G_PIN_TX_TRAINEN2     ,   /* PIN_TX_TRAIN_ENABLE2 */
    DKIT_AT56G_PIN_TX_TRAINEN3     ,   /* PIN_TX_TRAIN_ENABLE3 */
    DKIT_AT56G_PIN_TX_TRAINCO0     ,   /* PIN_TX_TRAIN_COMPLETE0 */
    DKIT_AT56G_PIN_TX_TRAINCO1     ,   /* PIN_TX_TRAIN_COMPLETE1 */
    DKIT_AT56G_PIN_TX_TRAINCO2     ,   /* PIN_TX_TRAIN_COMPLETE2 */
    DKIT_AT56G_PIN_TX_TRAINCO3     ,   /* PIN_TX_TRAIN_COMPLETE3 */
    DKIT_AT56G_PIN_TX_TRAINFA0     ,   /* PIN_TX_TRAIN_FAILED0 */
    DKIT_AT56G_PIN_TX_TRAINFA1     ,   /* PIN_TX_TRAIN_FAILED1 */
    DKIT_AT56G_PIN_TX_TRAINFA2     ,   /* PIN_TX_TRAIN_FAILED2 */
    DKIT_AT56G_PIN_TX_TRAINFA3     ,   /* PIN_TX_TRAIN_FAILED3 */
    DKIT_AT56G_PIN_SQ_DET_LPF0     ,   /* PIN_SQ_DETECTED_LPF0 */
    DKIT_AT56G_PIN_SQ_DET_LPF1     ,   /* PIN_SQ_DETECTED_LPF1 */
    DKIT_AT56G_PIN_SQ_DET_LPF2     ,   /* PIN_SQ_DETECTED_LPF2 */
    DKIT_AT56G_PIN_SQ_DET_LPF3     ,   /* PIN_SQ_DETECTED_LPF3 */
    DKIT_AT56G_PIN_RX_INIT0        ,
    DKIT_AT56G_PIN_RX_INIT1        ,
    DKIT_AT56G_PIN_RX_INIT2        ,
    DKIT_AT56G_PIN_RX_INIT3        ,
    DKIT_AT56G_PIN_RX_INITDON0     ,   /* PIN_RX_INIT_DONE0 */
    DKIT_AT56G_PIN_RX_INITDON1     ,   /* PIN_RX_INIT_DONE1 */
    DKIT_AT56G_PIN_RX_INITDON2     ,   /* PIN_RX_INIT_DONE2 */
    DKIT_AT56G_PIN_RX_INITDON3     ,   /* PIN_RX_INIT_DONE3 */
    DKIT_AT56G_PIN_AVDD_SEL        ,
    DKIT_AT56G_PIN_SPD_CFG         ,
    DKIT_AT56G_PIN_PIPE_SEL        ,
    DKIT_AT56G_PIN_PRAM_RESET      ,   /*HssPramCfg, cfgPramReset*/
    DKIT_AT56G_PIN_PRAM_SOC_EN     ,   /**/
    DKIT_AT56G_PIN_TX_RST0         ,   /*HssCmnCfg, cfgHssTxRstLane0*/
    DKIT_AT56G_PIN_TX_RST1         ,   /*HssCmnCfg, cfgHssTxRstLane1*/
    DKIT_AT56G_PIN_TX_RST2         ,   /*HssCmnCfg, cfgHssTxRstLane2*/
    DKIT_AT56G_PIN_TX_RST3         ,   /*HssCmnCfg, cfgHssTxRstLane3*/
    DKIT_AT56G_PIN_RX_RST0         ,   /*HssCmnCfg, cfgHssRxRstLane0*/
    DKIT_AT56G_PIN_RX_RST1         ,   /*HssCmnCfg, cfgHssRxRstLane1*/
    DKIT_AT56G_PIN_RX_RST2         ,   /*HssCmnCfg, cfgHssRxRstLane2*/
    DKIT_AT56G_PIN_RX_RST3         ,   /*HssCmnCfg, cfgHssRxRstLane3*/
    DKIT_AT56G_PIN_FW_READY        ,   /*HssCmnCfg, cfgHssFwReady*/
    DKIT_AT56G_PIN_PLL_RDY_RX0     ,   /*HssMon, monHssPllReadyRxLane0*/
    DKIT_AT56G_PIN_PLL_RDY_RX1     ,   /*HssMon, monHssPllReadyRxLane1*/
    DKIT_AT56G_PIN_PLL_RDY_RX2     ,   /*HssMon, monHssPllReadyRxLane2*/
    DKIT_AT56G_PIN_PLL_RDY_RX3     ,   /*HssMon, monHssPllReadyRxLane3*/
    DKIT_AT56G_PIN_PLL_RDY_TX0     ,   /*HssMon, monHssPllReadyTxLane0*/
    DKIT_AT56G_PIN_PLL_RDY_TX1     ,   /*HssMon, monHssPllReadyTxLane1*/
    DKIT_AT56G_PIN_PLL_RDY_TX2     ,   /*HssMon, monHssPllReadyTxLane2*/
    DKIT_AT56G_PIN_PLL_RDY_TX3     ,   /*HssMon, monHssPllReadyTxLane3*/
    DKIT_AT56G_PIN_TX_RST_ACK0     ,   /*HssMon, monHssTxRstAckLane0*/
    DKIT_AT56G_PIN_TX_RST_ACK1     ,   /*HssMon, monHssTxRstAckLane1*/
    DKIT_AT56G_PIN_TX_RST_ACK2     ,   /*HssMon, monHssTxRstAckLane2*/
    DKIT_AT56G_PIN_TX_RST_ACK3     ,   /*HssMon, monHssTxRstAckLane3*/
    DKIT_AT56G_PIN_RX_RST_ACK0     ,   /*HssMon, monHssRxRstAckLane0*/
    DKIT_AT56G_PIN_RX_RST_ACK1     ,   /*HssMon, monHssRxRstAckLane1*/
    DKIT_AT56G_PIN_RX_RST_ACK2     ,   /*HssMon, monHssRxRstAckLane2*/
    DKIT_AT56G_PIN_RX_RST_ACK3     ,   /*HssMon, monHssRxRstAckLane3*/
    DKIT_AT56G_PIN_RX_GRAYCODE_EN0 ,   /*HssRxCfg, cfgHssRxGrayCodeEnLane0*/
    DKIT_AT56G_PIN_RX_GRAYCODE_EN1 ,   /*HssRxCfg, cfgHssRxGrayCodeEnLane1*/
    DKIT_AT56G_PIN_RX_GRAYCODE_EN2 ,   /*HssRxCfg, cfgHssRxGrayCodeEnLane2*/
    DKIT_AT56G_PIN_RX_GRAYCODE_EN3 ,   /*HssRxCfg, cfgHssRxGrayCodeEnLane3*/
    DKIT_AT56G_PIN_TX_GRAYCODE_EN0 ,   /*HssTxCfg, cfgHssTxGrayCodeEnLane0*/
    DKIT_AT56G_PIN_TX_GRAYCODE_EN1 ,   /*HssTxCfg, cfgHssTxGrayCodeEnLane1*/
    DKIT_AT56G_PIN_TX_GRAYCODE_EN2 ,   /*HssTxCfg, cfgHssTxGrayCodeEnLane2*/
    DKIT_AT56G_PIN_TX_GRAYCODE_EN3 ,   /*HssTxCfg, cfgHssTxGrayCodeEnLane3*/
    DKIT_AT56G_PIN_RX_PRECODE_EN0  ,   /*HssRxCfg, cfgHssRxPreCodeEnLane0*/
    DKIT_AT56G_PIN_RX_PRECODE_EN1  ,   /*HssRxCfg, cfgHssRxPreCodeEnLane1*/
    DKIT_AT56G_PIN_RX_PRECODE_EN2  ,   /*HssRxCfg, cfgHssRxPreCodeEnLane2*/
    DKIT_AT56G_PIN_RX_PRECODE_EN3  ,   /*HssRxCfg, cfgHssRxPreCodeEnLane3*/
    DKIT_AT56G_PIN_TX_PRECODE_EN0  ,   /*HssTxCfg, cfgHssTxPreCodeEnLane0*/
    DKIT_AT56G_PIN_TX_PRECODE_EN1  ,   /*HssTxCfg, cfgHssTxPreCodeEnLane1*/
    DKIT_AT56G_PIN_TX_PRECODE_EN2  ,   /*HssTxCfg, cfgHssTxPreCodeEnLane2*/
    DKIT_AT56G_PIN_TX_PRECODE_EN3  ,   /*HssTxCfg, cfgHssTxPreCodeEnLane3*/
    DKIT_AT56G_PIN_RX_DTL_CLAMP0   ,   /*HssMon, monHssRxDtlClampLane0*/
    DKIT_AT56G_PIN_RX_DTL_CLAMP1   ,   /*HssMon, monHssRxDtlClampLane1*/
    DKIT_AT56G_PIN_RX_DTL_CLAMP2   ,   /*HssMon, monHssRxDtlClampLane2*/
    DKIT_AT56G_PIN_RX_DTL_CLAMP3   ,   /*HssMon, monHssRxDtlClampLane3*/
    DKIT_AT56G_PIN_FORCE_PMA_RDY_EN0  ,   /*HssLaneCfg, cfgForcePmaReady4PcsEnLane0*/
    DKIT_AT56G_PIN_FORCE_PMA_RDY_EN1  ,   /*HssLaneCfg, cfgForcePmaReady4PcsEnLane1*/
    DKIT_AT56G_PIN_FORCE_PMA_RDY_EN2  ,   /*HssLaneCfg, cfgForcePmaReady4PcsEnLane2*/
    DKIT_AT56G_PIN_FORCE_PMA_RDY_EN3  ,   /*HssLaneCfg, cfgForcePmaReady4PcsEnLane3*/
    DKIT_AT56G_PIN_FORCE_PMA_RDY_VAL0 ,   /*HssLaneCfg, cfgForcePmaReady4PcsEnLane0*/
    DKIT_AT56G_PIN_FORCE_PMA_RDY_VAL1 ,   /*HssLaneCfg, cfgForcePmaReady4PcsEnLane1*/
    DKIT_AT56G_PIN_FORCE_PMA_RDY_VAL2 ,   /*HssLaneCfg, cfgForcePmaReady4PcsEnLane2*/
    DKIT_AT56G_PIN_FORCE_PMA_RDY_VAL3 ,   /*HssLaneCfg, cfgForcePmaReady4PcsEnLane3*/
    DKIT_AT56G_PIN_PRAM_CHECKSUM_RESET,   /*HssPramCfg, cfgPramChecksumReset*/
    DKIT_AT56G_PIN_PRAM_CHECKSUM      ,   /*HssPramMon, monPramChecksum*/
    DKIT_AT56G_PIN_PRAM_CHECKSUM_EN   ,   /*HssPramCfg, cfgPramChecksumEn*/
    DKIT_AT56G_PIN_PRAM_CHECKSUM_SEL  ,   /*HssPramCfg, cfgPramChecksumSel*/
    DKIT_AT56G_PIN_MCU_INIT_DONE      ,   /*HssMcuMon, monHssMcuInitDone*/

    DKIT_AT56G_PIN_NUM
} _ctc_at_dkit_serdes_56g_pin_e;


typedef enum
{
    DKIT_AT112G_PIN_RESET            = 0,
    DKIT_AT112G_PIN_ISOLATION        ,
    DKIT_AT112G_PIN_BG_RDY           ,
    DKIT_AT112G_PIN_SIF_SEL          ,
    DKIT_AT112G_PIN_MCU_CLK          ,
    DKIT_AT112G_PIN_DIRECTACCESS     ,    /* PIN_DIRECT_ACCESS_EN */
    DKIT_AT112G_PIN_PRAM_FORCE       ,    /* PIN_PRAM_FORCE_RESET */
    DKIT_AT112G_PIN_PRAM_RESET       ,
    DKIT_AT112G_PIN_PRAM_SOC_EN      ,
    DKIT_AT112G_PIN_PRAM_SIF_SEL     ,
    DKIT_AT112G_PIN_PHY_MODE         ,
    DKIT_AT112G_PIN_REFCLK_TX0       ,   /* PIN_REFCLK_SEL_TX0 */
    DKIT_AT112G_PIN_REFCLK_TX1       ,   /* PIN_REFCLK_SEL_TX1 */
    DKIT_AT112G_PIN_REFCLK_TX2       ,   /* PIN_REFCLK_SEL_TX2 */
    DKIT_AT112G_PIN_REFCLK_TX3       ,   /* PIN_REFCLK_SEL_TX3 */
    DKIT_AT112G_PIN_REFCLK_RX0       ,   /* PIN_REFCLK_SEL_RX0 */
    DKIT_AT112G_PIN_REFCLK_RX1       ,   /* PIN_REFCLK_SEL_RX1 */
    DKIT_AT112G_PIN_REFCLK_RX2       ,   /* PIN_REFCLK_SEL_RX2 */
    DKIT_AT112G_PIN_REFCLK_RX3       ,   /* PIN_REFCLK_SEL_RX3 */
    DKIT_AT112G_PIN_REF_FREF_TX0     ,   /* PIN_REF_FREF_TX0 */
    DKIT_AT112G_PIN_REF_FREF_TX1     ,   /* PIN_REF_FREF_TX1 */
    DKIT_AT112G_PIN_REF_FREF_TX2     ,   /* PIN_REF_FREF_TX2 */
    DKIT_AT112G_PIN_REF_FREF_TX3     ,   /* PIN_REF_FREF_TX3 */
    DKIT_AT112G_PIN_REF_FREF_RX0     ,   /* PIN_REF_FREF_RX0 */
    DKIT_AT112G_PIN_REF_FREF_RX1     ,   /* PIN_REF_FREF_RX1 */
    DKIT_AT112G_PIN_REF_FREF_RX2     ,   /* PIN_REF_FREF_RX2 */
    DKIT_AT112G_PIN_REF_FREF_RX3     ,   /* PIN_REF_FREF_RX3 */
    DKIT_AT112G_PIN_PHY_GEN_TX0      ,
    DKIT_AT112G_PIN_PHY_GEN_TX1      ,
    DKIT_AT112G_PIN_PHY_GEN_TX2      ,
    DKIT_AT112G_PIN_PHY_GEN_TX3      ,
    DKIT_AT112G_PIN_PHY_GEN_RX0      ,
    DKIT_AT112G_PIN_PHY_GEN_RX1      ,
    DKIT_AT112G_PIN_PHY_GEN_RX2      ,
    DKIT_AT112G_PIN_PHY_GEN_RX3      ,
    DKIT_AT112G_PIN_PU_PLL0          ,
    DKIT_AT112G_PIN_PU_PLL1          ,
    DKIT_AT112G_PIN_PU_PLL2          ,
    DKIT_AT112G_PIN_PU_PLL3          ,
    DKIT_AT112G_PIN_PU_RX0           ,
    DKIT_AT112G_PIN_PU_RX1           ,
    DKIT_AT112G_PIN_PU_RX2           ,
    DKIT_AT112G_PIN_PU_RX3           ,
    DKIT_AT112G_PIN_PU_TX0           ,
    DKIT_AT112G_PIN_PU_TX1           ,
    DKIT_AT112G_PIN_PU_TX2           ,
    DKIT_AT112G_PIN_PU_TX3           ,
    DKIT_AT112G_PIN_TX_IDLE0         ,
    DKIT_AT112G_PIN_TX_IDLE1         ,
    DKIT_AT112G_PIN_TX_IDLE2         ,
    DKIT_AT112G_PIN_TX_IDLE3         ,
    DKIT_AT112G_PIN_PU_IVREF         ,
    DKIT_AT112G_PIN_RX_TRAIN_EN0     ,   /* PIN_RX_TRAIN_ENABLE0 */
    DKIT_AT112G_PIN_RX_TRAIN_EN1     ,   /* PIN_RX_TRAIN_ENABLE1 */
    DKIT_AT112G_PIN_RX_TRAIN_EN2     ,   /* PIN_RX_TRAIN_ENABLE2 */
    DKIT_AT112G_PIN_RX_TRAIN_EN3     ,   /* PIN_RX_TRAIN_ENABLE3 */
    DKIT_AT112G_PIN_RX_TRAIN_CO0     ,   /* PIN_RX_TRAIN_COMPLETE0 */
    DKIT_AT112G_PIN_RX_TRAIN_CO1     ,   /* PIN_RX_TRAIN_COMPLETE1 */
    DKIT_AT112G_PIN_RX_TRAIN_CO2     ,   /* PIN_RX_TRAIN_COMPLETE2 */
    DKIT_AT112G_PIN_RX_TRAIN_CO3     ,   /* PIN_RX_TRAIN_COMPLETE3 */
    DKIT_AT112G_PIN_RX_TRAIN_FA0     ,   /* PIN_RX_TRAIN_FAILED0 */
    DKIT_AT112G_PIN_RX_TRAIN_FA1     ,   /* PIN_RX_TRAIN_FAILED1 */
    DKIT_AT112G_PIN_RX_TRAIN_FA2     ,   /* PIN_RX_TRAIN_FAILED2 */
    DKIT_AT112G_PIN_RX_TRAIN_FA3     ,   /* PIN_RX_TRAIN_FAILED3 */
    DKIT_AT112G_PIN_TX_TRAIN_EN0     ,   /* PIN_TX_TRAIN_ENABLE0 */
    DKIT_AT112G_PIN_TX_TRAIN_EN1     ,   /* PIN_TX_TRAIN_ENABLE1 */
    DKIT_AT112G_PIN_TX_TRAIN_EN2     ,   /* PIN_TX_TRAIN_ENABLE2 */
    DKIT_AT112G_PIN_TX_TRAIN_EN3     ,   /* PIN_TX_TRAIN_ENABLE3 */
    DKIT_AT112G_PIN_TX_TRAIN_CO0     ,   /* PIN_TX_TRAIN_COMPLETE0 */
    DKIT_AT112G_PIN_TX_TRAIN_CO1     ,   /* PIN_TX_TRAIN_COMPLETE1 */
    DKIT_AT112G_PIN_TX_TRAIN_CO2     ,   /* PIN_TX_TRAIN_COMPLETE2 */
    DKIT_AT112G_PIN_TX_TRAIN_CO3     ,   /* PIN_TX_TRAIN_COMPLETE3 */
    DKIT_AT112G_PIN_TX_TRAIN_FA0     ,   /* PIN_TX_TRAIN_FAILED0 */
    DKIT_AT112G_PIN_TX_TRAIN_FA1     ,   /* PIN_TX_TRAIN_FAILED1 */
    DKIT_AT112G_PIN_TX_TRAIN_FA2     ,   /* PIN_TX_TRAIN_FAILED2 */
    DKIT_AT112G_PIN_TX_TRAIN_FA3     ,   /* PIN_TX_TRAIN_FAILED3 */
    DKIT_AT112G_PIN_SQ_DET_LPF0      ,   /* PIN_SQ_DETECTED_LPF0 */
    DKIT_AT112G_PIN_SQ_DET_LPF1      ,   /* PIN_SQ_DETECTED_LPF1 */
    DKIT_AT112G_PIN_SQ_DET_LPF2      ,   /* PIN_SQ_DETECTED_LPF2 */
    DKIT_AT112G_PIN_SQ_DET_LPF3      ,   /* PIN_SQ_DETECTED_LPF3 */
    DKIT_AT112G_PIN_RX_INIT0         ,
    DKIT_AT112G_PIN_RX_INIT1         ,
    DKIT_AT112G_PIN_RX_INIT2         ,
    DKIT_AT112G_PIN_RX_INIT3         ,
    DKIT_AT112G_PIN_RX_INITDONE0     ,   /* PIN_RX_INIT_DONE0 */
    DKIT_AT112G_PIN_RX_INITDONE1     ,   /* PIN_RX_INIT_DONE1 */
    DKIT_AT112G_PIN_RX_INITDONE2     ,   /* PIN_RX_INIT_DONE2 */
    DKIT_AT112G_PIN_RX_INITDONE3     ,   /* PIN_RX_INIT_DONE3 */
    DKIT_AT112G_PIN_AVDD_SEL         ,
    DKIT_AT112G_PIN_SPD_CFG          ,
    DKIT_AT112G_PIN_TX_RST0          ,   /*HssCmnCfg, cfgHssTxRstLane0*/
    DKIT_AT112G_PIN_TX_RST1          ,   /*HssCmnCfg, cfgHssTxRstLane1*/
    DKIT_AT112G_PIN_TX_RST2          ,   /*HssCmnCfg, cfgHssTxRstLane2*/
    DKIT_AT112G_PIN_TX_RST3          ,   /*HssCmnCfg, cfgHssTxRstLane3*/
    DKIT_AT112G_PIN_RX_RST0          ,   /*HssCmnCfg, cfgHssRxRstLane0*/
    DKIT_AT112G_PIN_RX_RST1          ,   /*HssCmnCfg, cfgHssRxRstLane1*/
    DKIT_AT112G_PIN_RX_RST2          ,   /*HssCmnCfg, cfgHssRxRstLane2*/
    DKIT_AT112G_PIN_RX_RST3          ,   /*HssCmnCfg, cfgHssRxRstLane3*/
    DKIT_AT112G_PIN_FW_READY         ,   /*HssCmnCfg, cfgHssFwReady*/
    DKIT_AT112G_PIN_PLL_RDY_RX0      ,   /*HssMon, monHssPllReadyRxLane0*/
    DKIT_AT112G_PIN_PLL_RDY_RX1      ,   /*HssMon, monHssPllReadyRxLane1*/
    DKIT_AT112G_PIN_PLL_RDY_RX2      ,   /*HssMon, monHssPllReadyRxLane2*/
    DKIT_AT112G_PIN_PLL_RDY_RX3      ,   /*HssMon, monHssPllReadyRxLane3*/
    DKIT_AT112G_PIN_PLL_RDY_TX0      ,   /*HssMon, monHssPllReadyTxLane0*/
    DKIT_AT112G_PIN_PLL_RDY_TX1      ,   /*HssMon, monHssPllReadyTxLane1*/
    DKIT_AT112G_PIN_PLL_RDY_TX2      ,   /*HssMon, monHssPllReadyTxLane2*/
    DKIT_AT112G_PIN_PLL_RDY_TX3      ,   /*HssMon, monHssPllReadyTxLane3*/
    DKIT_AT112G_PIN_TX_RST_ACK0      ,   /*HssMon, monHssTxRstAckLane0*/
    DKIT_AT112G_PIN_TX_RST_ACK1      ,   /*HssMon, monHssTxRstAckLane1*/
    DKIT_AT112G_PIN_TX_RST_ACK2      ,   /*HssMon, monHssTxRstAckLane2*/
    DKIT_AT112G_PIN_TX_RST_ACK3      ,   /*HssMon, monHssTxRstAckLane3*/
    DKIT_AT112G_PIN_RX_RST_ACK0      ,   /*HssMon, monHssRxRstAckLane0*/
    DKIT_AT112G_PIN_RX_RST_ACK1      ,   /*HssMon, monHssRxRstAckLane1*/
    DKIT_AT112G_PIN_RX_RST_ACK2      ,   /*HssMon, monHssRxRstAckLane2*/
    DKIT_AT112G_PIN_RX_RST_ACK3      ,   /*HssMon, monHssRxRstAckLane3*/
    DKIT_AT112G_PIN_RX_GRAYCODE_EN0  ,   /*HssRxCfg, cfgHssRxGrayCodeEnLane0*/
    DKIT_AT112G_PIN_RX_GRAYCODE_EN1  ,   /*HssRxCfg, cfgHssRxGrayCodeEnLane1*/
    DKIT_AT112G_PIN_RX_GRAYCODE_EN2  ,   /*HssRxCfg, cfgHssRxGrayCodeEnLane2*/
    DKIT_AT112G_PIN_RX_GRAYCODE_EN3  ,   /*HssRxCfg, cfgHssRxGrayCodeEnLane3*/
    DKIT_AT112G_PIN_TX_GRAYCODE_EN0  ,   /*HssTxCfg, cfgHssTxGrayCodeEnLane0*/
    DKIT_AT112G_PIN_TX_GRAYCODE_EN1  ,   /*HssTxCfg, cfgHssTxGrayCodeEnLane1*/
    DKIT_AT112G_PIN_TX_GRAYCODE_EN2  ,   /*HssTxCfg, cfgHssTxGrayCodeEnLane2*/
    DKIT_AT112G_PIN_TX_GRAYCODE_EN3  ,   /*HssTxCfg, cfgHssTxGrayCodeEnLane3*/
    DKIT_AT112G_PIN_RX_PRECODE_EN0   ,   /*HssRxCfg, cfgHssRxPreCodeEnLane0*/
    DKIT_AT112G_PIN_RX_PRECODE_EN1   ,   /*HssRxCfg, cfgHssRxPreCodeEnLane1*/
    DKIT_AT112G_PIN_RX_PRECODE_EN2   ,   /*HssRxCfg, cfgHssRxPreCodeEnLane2*/
    DKIT_AT112G_PIN_RX_PRECODE_EN3   ,   /*HssRxCfg, cfgHssRxPreCodeEnLane3*/
    DKIT_AT112G_PIN_TX_PRECODE_EN0   ,   /*HssTxCfg, cfgHssTxPreCodeEnLane0*/
    DKIT_AT112G_PIN_TX_PRECODE_EN1   ,   /*HssTxCfg, cfgHssTxPreCodeEnLane1*/
    DKIT_AT112G_PIN_TX_PRECODE_EN2   ,   /*HssTxCfg, cfgHssTxPreCodeEnLane2*/
    DKIT_AT112G_PIN_TX_PRECODE_EN3   ,   /*HssTxCfg, cfgHssTxPreCodeEnLane3*/
    DKIT_AT112G_PIN_FORCE_PMA_RDY_EN0     ,   /*HssLaneCfg, cfgForcePmaReady4PcsEnLane0*/
    DKIT_AT112G_PIN_FORCE_PMA_RDY_EN1,   /*HssLaneCfg, cfgForcePmaReady4PcsEnLane1*/
    DKIT_AT112G_PIN_FORCE_PMA_RDY_EN2,   /*HssLaneCfg, cfgForcePmaReady4PcsEnLane2*/
    DKIT_AT112G_PIN_FORCE_PMA_RDY_EN3,   /*HssLaneCfg, cfgForcePmaReady4PcsEnLane3*/
    DKIT_AT112G_PIN_FORCE_PMA_RDY_VAL0,   /*HssLaneCfg, cfgForcePmaReady4PcsValueLane0*/
    DKIT_AT112G_PIN_FORCE_PMA_RDY_VAL1,   /*HssLaneCfg, cfgForcePmaReady4PcsValueLane1*/
    DKIT_AT112G_PIN_FORCE_PMA_RDY_VAL2,   /*HssLaneCfg, cfgForcePmaReady4PcsValueLane2*/
    DKIT_AT112G_PIN_FORCE_PMA_RDY_VAL3,   /*HssLaneCfg, cfgForcePmaReady4PcsValueLane3*/
    DKIT_AT112G_PIN_PRAM_CHECKSUM_RESET,   /*HssPramCfg, cfgPramChecksumReset*/
    DKIT_AT112G_PIN_PRAM_CHECKSUM      ,   /*HssPramMon, monPramChecksum*/
    DKIT_AT112G_PIN_PRAM_CHECKSUM_EN   ,   /*HssPramCfg, cfgPramChecksumEn*/
    DKIT_AT112G_PIN_PRAM_CHECKSUM_SEL  ,   /*HssPramCfg, cfgPramChecksumSel*/
    DKIT_AT112G_PIN_MCU_INIT_DONE      ,   /*HssMcuMon, monHssMcuInitDone*/
    DKIT_AT112G_PIN_RX_DTL_CLAMP0    ,
    DKIT_AT112G_PIN_RX_DTL_CLAMP1    ,
    DKIT_AT112G_PIN_RX_DTL_CLAMP2    ,
    DKIT_AT112G_PIN_RX_DTL_CLAMP3    ,

    DKIT_AT112G_PIN_NUM
} _sys_at_serdes_112g_pin_e;


uint32 at56g_reglist[][2]= {
    /* left bound , right bound*/
    {0x0000, 0x0500},
    {0x1000, 0x1b00},
    {0x2000, 0x2d00},
    {0x3000, 0x3600},
    {0x4000, 0x4300},
    {0x5000, 0x5a00},
    {0x6000, 0x6f00},
    {0x8000, 0x8500},
    {0xa200, 0xa500},
    {0xe600, 0xe800},
};

uint32 at112g_reglist[][2] = 
{
    {0x1000, 0x1ff0},
    {0x2000, 0x2d00},
    {0x3000, 0x3600},
    {0x4000, 0x4b00},
    {0x5000, 0x5900},
    {0x6000, 0x6400},
    {0x8000, 0x8500},
    {0xa200, 0xa500},
    {0xe600, 0xe700},
};
